Patents by Inventor Daniele Balluchi
Daniele Balluchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230297285Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.Type: ApplicationFiled: March 15, 2023Publication date: September 21, 2023Inventors: Amitava Majumdar, Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi, Chia Wei Chang, Ankush Lal
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Publication number: 20230290427Abstract: A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.Type: ApplicationFiled: March 10, 2023Publication date: September 14, 2023Inventors: Danilo Caraccio, Daniele Balluchi, Niccolò Izzo, Alessandro Orlando
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Publication number: 20230289270Abstract: An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direct control over the electronic device. Examples of the electronic device include a memory device and a power management integrated circuit. The electronic device can allow the host to discover a quantity of tests supported by the electronic device and corresponding test descriptors. The electronic device can interact with the host to configure tests and/or reporting of test results.Type: ApplicationFiled: March 14, 2023Publication date: September 14, 2023Inventors: Danilo Caraccio, Daniele Balluchi, Niccolò Izzo, Alessandro Orlando
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Patent number: 11741027Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.Type: GrantFiled: July 14, 2022Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Daniele Balluchi
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Patent number: 11742002Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.Type: GrantFiled: December 14, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Angelo Visconti, Daniele Balluchi, Giorgio Servalli
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Patent number: 11720163Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.Type: GrantFiled: July 21, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Greg Blodgett, Daniele Balluchi, Danilo Caraccio, Graziano Mirichigni
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Patent number: 11721395Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.Type: GrantFiled: November 3, 2021Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Daniele Balluchi
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Publication number: 20230236930Abstract: A system and method for memory error recovery in CXL components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.Type: ApplicationFiled: May 31, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Marc SFORZIN, Paolo AMATO, Daniele BALLUCHI
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Publication number: 20230236753Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.Type: ApplicationFiled: June 30, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Marco SFORZIN, Angelo VISCONTI, Giorgio SERVALLI, Daniele BALLUCHI, Paolo AMATO
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Publication number: 20230214119Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.Type: ApplicationFiled: September 29, 2022Publication date: July 6, 2023Inventors: Marco Sforzin, Paolo Amato, Daniele Balluchi
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Patent number: 11693781Abstract: A processing device in a memory system receives, from a host system, a read command comprising an indication of a sub-region of a logical address space of a memory device. The processing device increments a counter associated with a region of the logical address space, the region comprising a plurality of sub-regions including the sub-region, the counter to track a number of read operations performed on the plurality of sub-regions of the region, wherein the counter is periodically decremented in response to an occurrence of a recency event on the memory device. The processing device further determines whether a value of the counter satisfies a cacheable threshold criterion and, responsive to the value of the counter satisfying the cacheable threshold criterion, sends, to the host system, a recommendation to activate the sub-region.Type: GrantFiled: August 20, 2020Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Daniele Balluchi
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Patent number: 11687273Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.Type: GrantFiled: September 29, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Emanuele Confalonieri, Paolo Amato, Marco Sforzin, Danilo Caraccio, Daniele Balluchi
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Patent number: 11669461Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: GrantFiled: July 26, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Daniele Balluchi, Dionisio Minopoli
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Patent number: 11656983Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.Type: GrantFiled: May 17, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Daniele Balluchi, Dionisio Minopoli
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Publication number: 20230153204Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.Type: ApplicationFiled: January 20, 2023Publication date: May 18, 2023Inventors: Danilo Caraccio, Daniele Balluchi
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Publication number: 20230096375Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Emanuele Confalonieri, Paolo Amato, Marco Sforzin, Danilo Caraccio, Daniele Balluchi
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Publication number: 20230054662Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
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Patent number: 11579970Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.Type: GrantFiled: July 14, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Danilo Caraccio, Daniele Balluchi
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Publication number: 20230016520Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.Type: ApplicationFiled: July 10, 2022Publication date: January 19, 2023Inventors: Marco Sforzin, Daniele Balluchi
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Patent number: 11550678Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.Type: GrantFiled: March 19, 2021Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Marco Dallabora, Emanuele Confalonieri, Paolo Amato, Daniele Balluchi, Danilo Caraccio