Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between a first thread and a second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is shareable based on the alias table entry.

Abstract: The presently claimed invention relates to a polymer emulsion and a process for preparing a polymer emulsion. Particularly, the presently claimed invention relates to a process for preparing a polymer emulsion with high solids content.

Abstract: Disclosed is a cable assembly including at least one conductor and a metal sheath disposed over the at least one conductor, the metal sheath including a continuous strip of metal having a plurality of revolutions. A first revolution of the plurality of revolutions may include a first section having a curved profile extending into an interior cavity of the metal sheath, and a second section extending from the first section, the second section extending along a lengthwise axis, wherein a length of the second section, along the lengthwise axis, is at least two times as large as a diameter of the first section when the metal sheath is in a linear configuration. The first revolution may further include a third section extending from the second section, the third section including a free end terminating within a recess defined by a curved profile of a first section of an adjacent revolution.

Abstract: Estimating wear on bottom hole assembly (BHA) components utilizes a rock hardness index using analysis of drill cutting. Estimating the amount of wear on borehole assembly components comprises measuring the rock properties in drilled cuttings from a borehole. A hardness value is assigned to each mineral present in the drilled cuttings. A hardness index is calculated for a drilled borehole interval. A wear resistance factor is assigned to each BHA component of the BHA. The wear resistance factor depends on the wear resistance of each BHA component. A wear value for each BHA component is calculated based on the hardness index for the drilled borehole interval, the wear resistance of the BHA component, and drilling parameters.

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

Abstract: Provided herein are multispecific antibodies that selectively bind to PSMA and effector cell antigens such as CD3, pharmaceutical compositions thereof, as well as nucleic acids, and methods for making and discovering the same.

Abstract: Described herein are compounds and pharmaceutical compositions containing such compounds which inhibit transglutaminase 2 (TG2). Also described herein are methods for using such TG2 inhibitors, alone or in combination with other compounds, for treating diseases or conditions that would benefit from TG2 inhibition.

Abstract: A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between the first thread and the second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is sharable based on the alias table entry.

Abstract: Provided herein are cleavable linkers, pharmaceutical compositions thereof, as well as nucleic acids, and methods for making and discovering the same. The cleavable linkers described herein have improved efficacy and safety.

Abstract: A system and method of handling access demands in a virtual cache comprising, by a processing system, checking if a virtual cache access demand missed because of a synonym tagged in the virtual cache; in response to the virtual cache access demand missing because of a synonym tagged in the virtual cache, updating the virtual address tag in the virtual cache to a new virtual address tag; searching for additional synonyms tagged in the virtual cache; and in response to finding additional synonyms tagged in the virtual cache, updating the virtual address tag of the additional synonyms to the new virtual address tag.

Abstract: A copolymer includes a hydrophobic head segment and a random copolymer tail segment comprising hydrophobic blocks and ionizable blocks. Emulsion polymerization systems incorporate the copolymer as a surfactant.

Abstract: The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to generate a first prefetch request and a second prefetch request based on the demand access stream, to output the first prefetch request to a first translation lookaside buffer (TLB), and to output the second prefetch request to a second TLB that is different from the first TLB. The processor performs a first TLB lookup in the first TLB based on one of the demand access stream or the first prefetch request, and performs a second TLB lookup in the second TLB based on the second prefetch request.

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

Abstract: A gradiometer includes a at least one magnet attached to a beam. The magnet moves in response to a magnetic force. A sensing element is configured to measure movement or deflection of the beam or magnet. The gradiometer is configured to determine a gradient of a magnetic field acting on the first magnet based on movement of the magnet. The gradiometer can further measure higher order gradients.

Abstract: A system and method of effectively measuring a change in a gradient of a magnetic field. The systems include a first magnet and a second magnet mechanically coupled together and aligned along a polarization axis. The first magnet and the second magnet are positioned such that a pair of like magnetic poles of the first magnet and the second magnet face in opposite directions. Further, the first magnet and the second magnet are configured to move along the polarization axis in response to a magnetic field. A sensing system is configured to measure a change in a gradient of the magnetic field based on the movement of the first magnet and second magnet along the polarization axis in response to the magnetic field.

Abstract: The methods and assays described herein relate to detection, diagnosis, and treatment of lung cancer, e.g., by detecting the level of expression of certain miRNAs described herein and/or by therapeutically increasing the level of those miRNAs.