Abstract: A radio frequency (RF) power amplifier (PA) amplifying transistor of an RF PA stage and an RF PA temperature compensating bias transistor of the RF PA stage are disclosed. The RF PA amplifying transistor includes a first array of amplifying transistor elements and a second array of amplifying transistor elements. The RF PA temperature compensating bias transistor provides temperature compensation of bias of the RF PA amplifying transistor. Further, the RF PA temperature compensating bias transistor is located between the first array and the second array. As such, the RF PA temperature compensating bias transistor is thermally coupled to the first array and the second array. The RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor.

Abstract: A power amplifier (PA) envelope power supply, radio frequency (RF) PA circuitry, and a process to select a converter operating mode of the PA envelope power supply based on linearity requirements of the RF PA circuitry is disclosed. The PA envelope power supply operates in one of a first converter operating mode and a second converter operating mode. The process for selecting the converter operating mode is based on a required degree of linearity of the RF PA circuitry. The PA envelope power supply provides an envelope power supply signal to the RF PA circuitry. Selection of the converter operating mode may provide efficient operation of the PA envelope power supply and the envelope power supply signal needed for proper operation of the RF PA circuitry.

Abstract: The present disclosure relates to a direct current (DC)-DC converter, which includes a charge pump based radio frequency (RF) power amplifier (PA) envelope power supply and a charge pump based PA bias power supply. The DC-DC converter is coupled between RF PA circuitry and a DC power supply, such as a battery. As such, the PA envelope power supply provides an envelope power supply signal to the RF PA circuitry and the PA bias power supply provides a bias power supply signal to the RF PA circuitry. Both the PA envelope power supply and the PA bias power supply receive power via a DC power supply signal from the DC power supply. The PA envelope power supply includes a charge pump buck converter and the PA bias power supply includes a charge pump.

Abstract: Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.

Abstract: Circuitry, which includes multi-mode multi-band radio frequency (RF) power amplification circuitry, power amplifier (PA) control circuitry, and a PA-digital communications interface (DCI) is disclosed according to one embodiment of the circuitry. The PA control circuitry is coupled between the amplification circuitry and the PA-DCI, which is coupled to a digital communications bus, and configures the amplification circuitry. The amplification circuitry includes at least a first RF input and multiple RF outputs, such that at least some of the RF outputs are associated with multiple communications modes and at least some of the RF outputs are associated with multiple frequency bands. Configuration of the amplification circuitry associates one RF input with one RF output, and is correlated with configuration information defined by at least a first defined parameter set. The PA control circuitry stores at least a first look-up table (LUT), which provides the configuration information.

Abstract: Embodiments of the present disclosure relate to multi-mode multi-band radio frequency (RF) power amplifier (PA) circuitry, which includes a multi-mode multi-band quadrature RF PA coupled to multi-mode multi-band switching circuitry via a single output. The switching circuitry provides at least one non-linear mode output and multiple linear mode outputs. The non-linear mode output may be associated with at least one non-linear mode RF communications band and each linear mode output may be associated with a corresponding linear mode RF communications band. The outputs from the switching circuitry may be coupled to an antenna port via front-end aggregation circuitry. The quadrature nature of the quadrature PA path may provide tolerance for changes in antenna loading conditions.

Abstract: Radio Frequency (RF) signal conditioning circuitry, which includes RF detection circuitry and RF attenuation circuitry is disclosed. The RF detection circuitry receives and detects an RF sample signal to provide an RF detection signal. The RF attenuation circuitry has an attenuation circuitry input, and receives and attenuates the RF sample signal via the attenuation circuitry input to provide an attenuated RF signal. The RF attenuation circuitry presents an attenuation circuitry input impedance at the attenuation circuitry input. The attenuated RF signal and the RF detection signal are provided concurrently.

Abstract: A charge pump of a PA bias power supply, PA bias circuitry, and a process to optimize efficiency of the PA bias power supply are disclosed. The charge pump operates in one of multiple bias supply pump operating modes, which include at least a bias supply pump-up operating mode and a bias supply bypass operating mode. The process prevents selection of the bias supply bypass operating mode unless a DC power supply voltage is adequate to allow the PA bias circuitry to provide minimum output regulation voltage at a specified current. Otherwise, the bias supply pump-up operating mode is selected. The charge pump operates more efficiently in the bias supply bypass operating mode than in the bias supply pump-up operating mode; therefore, selection of the bias supply bypass operating mode, when possible, increases efficiency.

Abstract: The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Abstract: The present disclosure relates to a flexible direct current (DC)-DC converter, which includes a charge pump buck power supply and a buck power supply. The charge pump buck power supply and the buck power supply are voltage compatible with one another at respective output inductance nodes to provide flexibility. In one embodiment of the DC-DC converter, capacitances at the output inductance nodes are at least partially isolated from one another by using at least an isolating inductive element between the output inductance nodes to increase efficiency. In an alternate embodiment of the DC-DC converter, the output inductance nodes are coupled to one another, such that the charge pump buck power supply and the buck power supply share a first inductive element, thereby eliminating the isolating inductive element, which reduces size and cost but may also reduce efficiency.

Abstract: A split current current digital-to-analog converter (IDAC) and a radio frequency (RF) power amplifier (PA) stage are disclosed. The split current IDAC operates in a selected one of a group of DDS operating modes and provides a group of array bias signals based on the selected one of the group of DDS operating modes. Each of the group of array bias signals is a current signal. The RF PA stage includes a group of arrays of amplifying transistor elements. The RF PA stage biases at least one of the group of arrays of amplifying transistor elements based on the group of array bias signals. Further, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using at least one of the group of arrays of amplifying transistor elements that is biased.

Abstract: The present invention relates to a lumped cross-coupled Wilkinson circuit having a pair of magnetically cross-coupled inductive elements coupled to an isolation network. By magnetically cross-coupling the inductive elements, which have a mutual inductance, the inductance of each inductive element will be significantly less than the inductance of each inductive element in an equivalent lumped traditional Wilkinson combiner. Since the inductance of each inductive element is less, the size of each inductive element may be significantly smaller and the resistive loss of the each inductive element may be significantly smaller. In one embodiment of the present invention, the lumped cross-coupled Wilkinson circuit operates as a lumped cross-coupled Wilkinson combiner. In an alternate embodiment of the present invention, the lumped cross-coupled Wilkinson circuit operates as a lumped cross-coupled Wilkinson splitter.

Abstract: A sample-and-hold (SAH) current estimating circuit and a first switching power supply are disclosed. The first switching power supply provides a first switching power supply output signal based on a series switching element and a setpoint. The SAH current estimating circuit samples a voltage across the series switching element of the first switching power supply during an ON state of the series switching element and during a ramping signal peak to provide an SAH output signal based on an estimate of an output current of the first switching power supply output signal. The first switching power supply selects the ON state of the series switching element, such that during the ramping signal peak, the series switching element has a series current having a magnitude, which is about equal to a magnitude of the output current of the first switching power supply output signal.

Abstract: Radio frequency (RF) power amplifier (PA) circuitry, which transmits RF signals is disclosed. The RF PA circuitry includes a final stage, a final stage current digital-to-analog converter (IDAC), and a final stage temperature compensation circuit. A final stage current reference circuit may provide an uncompensated final stage reference current to the final stage temperature compensation circuit, which receives and temperature compensates the uncompensated final stage reference current to provide a final stage reference current. The final stage IDAC uses the final stage reference current in a digital-to-analog conversion to provide a final stage bias signal to bias the final stage. The temperature compensation provided by the final stage temperature compensation circuit is selectable.

Abstract: The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.

Abstract: An in-phase radio frequency (RF) power amplifier (PA) stage and a quadrature-phase RF PA stage are disclosed. The in-phase RF PA stage includes a first group of arrays of amplifying transistor elements and the quadrature-phase RF PA stage includes a second group of arrays of amplifying transistor elements. A group of array bias signals is based on a selected one of a group of DDS operating modes. Each of the group of array bias signals is a current signal. The in-phase RF PA stage biases at least one of the first group of arrays of amplifying transistor elements based on the group of array bias signals. Similarly, the quadrature-phase RF PA stage biases at least one of the second group of arrays of amplifying transistor elements based on the group of array bias signals.

Abstract: A power amplifier (PA) controller semiconductor die and a first radio frequency (RF) PA semiconductor die are disclosed. The PA controller semiconductor die includes a first electro-static discharge (ESD) protection circuit, which ESD protects and provides a first ESD protected signal. The RF PA semiconductor die receives the first ESD protected signal. In one embodiment of the PA controller semiconductor die, the first ESD protected signal is an envelope power supply signal. The PA controller semiconductor die may be a Silicon complementary metal-oxide-semiconductor (CMOS) semiconductor die and the RF PA semiconductor die may be a Gallium Arsenide semiconductor die.

Abstract: RF PA circuitry and a DC-DC converter, which includes an RF PA envelope power supply and DC-DC control circuitry, are disclosed. The PA envelope power supply provides an envelope power supply signal to the RF PA circuitry. The DC-DC control circuitry has a DC-DC look-up table (LUT) structure, which has at least a first DC-DC LUT. The DC-DC control circuitry uses DC-DC LUT index information as an index to the DC-DC LUT structure to obtain DC-DC converter operational control parameters. The DC-DC control circuitry then configures the PA envelope power supply using the DC-DC converter operational control parameters. Using the DC-DC LUT structure provides flexibility in configuring the DC-DC converter for different applications, for multiple static operating conditions, for multiple dynamic operating conditions, or any combination thereof.

Abstract: The present invention is a low series impedance directional power detector, which may be used to measure either forward or reverse power in a radio frequency (RF) circuit. The directional power detector includes current detection circuitry to directionally measure current, voltage detection circuitry to measure voltage, and combining circuitry to combine the directional RF current measurements and the RF voltage measurements into a combined RF measurement, which is indicative of directional power. The current detection circuitry and voltage detection circuitry apply any phase-shifts that are needed to detect power in the direction of interest and ignore power in the opposite direction when the directional power detector is presented with a complex load.