Patents by Inventor David Hwang

David Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250157861
    Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Applicant: VueReal Inc.
    Inventors: Gholamreza CHAJI, Ehsanollah FATHI, Hossein Zamani SIBONI, David HWANG
  • Patent number: 12237236
    Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 25, 2025
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi, Hossein Zamani Siboni, David Hwang
  • Publication number: 20250056828
    Abstract: Some implementations herein provide for a memory device and methods of formation. The memory device includes a plurality of storage cells arranged vertically and a plurality of corresponding gate all around transistors. Methods of forming the memory device include using a single trench to remove a liner material and form recesses that define cell contact lightly-doped drain regions of the gate all around transistors. Using the single trench to remove the liner material and form the recesses that define the cell contact lightly-doped drain region widths causes the cell contact lightly-doped drain regions to be formed having substantially similar widths.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 13, 2025
    Inventors: Si-Woo LEE, Yuichi YOKOYAMA, Scott E. SILLS, Gautham MUTHUSAMY, David HWANG, Yoshitaka NAKAMURA, Pavani Vamsi Krishna NITTALA, Yuanzhi MA, Glen H. WALTERS, Haitao LIU, Kamal M. KARDA
  • Patent number: 12196491
    Abstract: A controller includes a non-transitory computer readable medium configured to store information related to a target temperature of a wafer, a target temperature of a heating element, a temperature of the wafer, and a temperature of the heating element. The controller further includes a processor connected to the non-transitory computer readable medium, the processor configured to generate at least one heating signal during a baking process to adjust a duration of an entirety of the baking process in response to the temperature of the wafer and the temperature of the heating element.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzung-Chen Wu, Heng-Jen Lee, Ho-Yung David Hwang, Wen-Zhan Zhou
  • Publication number: 20240393051
    Abstract: A controller includes a non-transitory computer readable medium configured to store information related to a target temperature of a wafer, a target temperature of a heating element, a temperature of the wafer, and a temperature of the heating element. The controller further includes a processor connected to the non-transitory computer readable medium, the processor configured to generate at least one heating signal during a baking process to adjust a duration of an entirety of the baking process in response to the temperature of the wafer and the temperature of the heating element.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Tzung-Chen WU, Heng-Jen LEE, Ho-Yung David HWANG, Wen-Zhan ZHOU
  • Publication number: 20240379376
    Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Rajesh Prasad, Yung-Chen Lin, Zhiyu Huang, Fenglin Wang, Chi-I Lang, Hoyung David Hwang, Edwin A. Arevalo, KyuHa Shim
  • Patent number: 12025917
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Patent number: 12021168
    Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method of forming an LED involves forming a semiconductor structure on a substrate. The semiconductor structure includes a p-side semiconductor layer, an n-side semiconductor layer, and an active light emitting layer between the p-side semiconductor layer and the n-side semiconductor layer. The semiconductor structure is also formed to include a light outcoupling surface facing the substrate. The light outcoupling surface has a diameter less than twice an electron diffusion length of a material of the semiconductor structure. The method further involves implanting ions in an outer region of the semiconductor structure, then annealing the outer region after the ions have been implanted. The annealing causes the ions to intermix with atoms within the outer region, thereby increasing a bandgap of the outer region.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: June 25, 2024
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Thomas Lauermann, Stephan Lutgen, David Hwang
  • Publication number: 20240145625
    Abstract: A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 2, 2024
    Applicant: The Regents of the University of California
    Inventors: David Hwang, Matthew S. Wong, Shuji Nakamura
  • Publication number: 20240071773
    Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Lei Liao, Yichuan Ling, Zhiyu Huang, Hideyuki Kanzawa, Fenglin Wang, Rajesh Prasad, Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang, Lequn Liu
  • Publication number: 20240020114
    Abstract: The subject technology detects a code commit at a code repository. The subject technology sends a request for a build job to a build server. The subject technology determines that the build job is completed. The subject technology sends a training request and user token to a proxy authenticator. The subject technology determines determining that the user token is validated. The subject technology sends a training request and the user token to a training job manager. Further, the subject technology determines determining that the training job is completed.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Inventors: William STORY, David HWANG
  • Patent number: 11869807
    Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Lili Feng, Yuqiong Dai, Madhur Sachan, Regina Freed, Ho-yung David Hwang
  • Publication number: 20230395560
    Abstract: This disclosure is related to integrating microdevices into a system substrate. In particular the microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pads on the system substrate at a temperature that is below the melting point of the materials on the pads of the system substrate and microdevice pads. The present disclosure also relates to integrating vertical microdevices into a system substrate. The system substrate can have a backplane circuit as well. The integration covers the microdevices with dielectrics and couples the backplane through a VIA. The disclosure further relates to a method and structure of microdevice or optoelectronic devices that allows for misalignment adjustment. The microdevices comprise a stack of semiconductor layers that in configuration with electrodes, substrate, VIA's and size factors minimize misalignment.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 7, 2023
    Applicant: VueReal Inc.
    Inventors: Gholamreza CHAJI, Ehsanollah FATHI, Hossein Zamani SIBONI, Lauren LESERGENT, David HWANG, Pranav GAVIRNENI
  • Publication number: 20230384680
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 30, 2023
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Patent number: 11809863
    Abstract: The subject technology detects a code commit at a code repository. The subject technology sends a request for a build job to a build server. The subject technology determines that the build job is completed. The subject technology sends a training request and user token to a proxy authenticator. The subject technology determines determining that the user token is validated. The subject technology sends a training request and the user token to a training job manager. Further, the subject technology determines determining that the training job is completed.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: November 7, 2023
    Assignee: Stripe, Inc.
    Inventors: William Story, David Hwang
  • Publication number: 20230260856
    Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.
    Type: Application
    Filed: July 15, 2021
    Publication date: August 17, 2023
    Applicant: VueReal Inc.
    Inventors: Gholamreza CHAJI, Ehsanollah FATHI, Hossein Zamani SIBONI, David HWANG
  • Publication number: 20230215735
    Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.
    Type: Application
    Filed: November 14, 2022
    Publication date: July 6, 2023
    Inventors: Lei LIAO, Yung-chen LIN, Chi-I LANG, Ho-yung David HWANG
  • Patent number: 11677042
    Abstract: Disclosed herein are methods, systems, and apparatuses for an light emitting diode (LED) array apparatus. In some embodiments, the LED array apparatus may include a plurality of mesas etched from a layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, a active layer, and an N-type doped semiconductor layer. The LED array apparatus may also include one or more regrowth semiconductor layers, including a first regrowth semiconductor layer, which may be grown epitaxially over etched facets of the plurality of mesas. In some cases, for each mesa, the first regrowth semiconductor layer may overlay etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer, around an entire perimeter of the mesa.
    Type: Grant
    Filed: March 29, 2020
    Date of Patent: June 13, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Markus Broell, Michael Grundmann, David Hwang, Stephan Lutgen, Brian Matthew Mcskimming, Anurag Tyagi
  • Patent number: 11638374
    Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: April 25, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
  • Patent number: 11581457
    Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method includes increasing a bandgap in an outer region of a semiconductor layer by implanting ions in the outer region of the semiconductor layer and subsequently annealing the outer region of the semiconductor layer to intermix the ions with atoms within the outer region of the semiconductor layer. The semiconductor layer includes an active light emitting layer. A light outcoupling surface of the semiconductor layer has a diameter that is less than twice an electron diffusion length of the semiconductor layer. The outer region of the semiconductor layer extends from an outer surface of the semiconductor layer to a central region of the semiconductor layer that is shaded by a mask during the implanting of the ions.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 14, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Thomas Lauermann, Stephan Lutgen, David Hwang