Abstract: III-V micro light-emitting diodes (LEDs) are fabricated using a photoelectrochemical (PEC) etch. A sacrificial layer and III-V device layers are epitaxially grown on a host substrate, wherein the III-V device layers are patterned to form the micro-LEDs. The sacrificial layer is removed by a photoelectrochemical (PEC) etch, so as to fully or partially separate the micro-LEDs from the substrate, before or after the micro-LEDs are bonded to a submount or intermediate substrate. The micro-LEDs may be bonded to a submount with a polymer film deposited thereon, wherein the polymer film with the micro-LEDs is subsequently delaminated from the submount. Alternatively, the intermediate substrate may be a transfer medium, wherein the micro-LEDs are separated from the host substrate by mechanical fracturing, and then bonded to a second substrate, after which the intermediate substrate is removed, wherein a third substrate may be bonded to exposed surfaces of the transferred micro-LEDs.

Abstract: A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.

Abstract: A method and apparatus for forming a crystalline cadmium stannate layer of a photovoltaic device by heating an amorphous layer in the presence of hydrogen gas.

Abstract: A compact LIDAR pointing assembly can comprise a body, first and second ferrules, and a clip component that can be used to maintain an engagement between the first and second ferrules and an alignment of light emanating from the first and second ferrules relative to received light propagating along an optical axis of the assembly. The ferrules can be pivoted to adjust the orientation of the light emanating from the ferrules.

Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.

Abstract: A method and apparatus for providing a route recommendation are disclosed. For example, the method obtains network topology information, wherein the network topology information comprises a plurality of underlying subnetwork types for a network. The method creates a cost model for the network, and receives a request from a user for a connection to be supported by the network. The method provides the route recommendation for supporting the connection by applying the cost model.

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract: A method and system for real-time, in-line calculations of opto-electronic properties and thickness of the layers of multi-layered transparent conductive oxide stacks of photovoltaic devices is provided. The method and system include taking measurements of each layer of the stack during deposition thereof. The measurements are then used to calculate the opto-electronic properties and thicknesses of the layers in real-time.

Abstract: A method and apparatus for forming a crystalline cadmium stannate layer of a photovoltaic device by heating an amorphous layer in the presence of hydrogen gas.

Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A compact LIDAR pointing assembly can comprise a body, first and second ferrules, and a clip component that can be used to maintain an engagement between the first and second ferrules and an alignment of light emanating from the first and second ferrules relative to received light propagating along an optical axis of the assembly. The ferrules can be pivoted to adjust the orientation of the light emanating from the ferrules.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.

Abstract: An adaptive baking system includes a baking chamber configured to receive a wafer, and a heating element configured to support the wafer. The adaptive baking system further includes a controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

Abstract: A method and apparatus for providing a route recommendation are disclosed. For example, the method obtains network topology information, wherein the network topology information comprises a plurality of underlying subnetwork types for a network. The method creates a cost model for the network, and receives a request from a user for a connection to be supported by the network. The method provides the route recommendation for supporting the connection by applying the cost model.

Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.

Abstract: A method and apparatus for providing a route recommendation are disclosed. For example, the method obtains network topology information, wherein the network topology information comprises a plurality of underlying subnetwork types for a network. The method creates a cost model for the network, and receives a request from a user for a connection to be supported by the network. The method provides the route recommendation for supporting the connection by applying the cost model.

Abstract: A method to improve operation of a CdTe-based photovoltaic device is disclosed, the method comprising the steps of depositing a semiconductor absorber layer adjacent to a substrate, depositing a semiconductor buffer layer adjacent to the semiconductor layer, and annealing at least one of the semiconductor absorber layer and the semiconductor buffer layer with one of a laser and a flash lamp.

Abstract: A photovoltaic device is disclosed, the device having a zinc-containing layer, such as a ZnO1-xSx layer, as a window layer, as part of a composite window layer, and/or as a buffer layer. Use of the ZnO1-xSx layer improves an overall efficiency of the photovoltaic device due to improved optical transmission thereof as compared to CdS window layers, and due to a improved quantum efficiency of the photovoltaic device in the blue light spectrum due to the presence of the ZnO1-xSx layer.