Patents by Inventor David H. Wells

David H. Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for forming arrays of small, closely spaced features
    Patent number: 8266558
    Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells
    Publication number: 20120187363
    Abstract: A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Inventors: Zengtao T. Liu, David H. Wells
  • CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY
    Publication number: 20120182787
    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
    Type: Application
    Filed: March 27, 2012
    Publication date: July 19, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Jun Liu
  • METHODS OF FORMING SINGLE CRYSTAL SILICON STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SINGLE CRYSTAL SILICON STRUCTURES
    Publication number: 20120168898
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Memory cell, pair of memory cells, and memory array
    Patent number: 8207564
    Abstract: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The shared digitline couples with adjacent memory cells, and the plurality of access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in a substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, David H. Wells
  • Reverse construction memory cell
    Patent number: 8187934
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Single crystal silicon structures
    Patent number: 8159050
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array
    Patent number: 8144506
    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Jun Liu
  • Integrated circuit with buried digit line
    Patent number: 8102008
    Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY
    Publication number: 20110272660
    Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON AND METHOD OF FORMING SAME
    Publication number: 20110260298
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Application
    Filed: July 5, 2011
    Publication date: October 27, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
  • Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry
    Publication number: 20110256694
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: June 9, 2011
    Publication date: October 20, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: David H. Wells
  • Integrated circuitry and methods of forming a semiconductor-on-insulator substrate
    Patent number: 8039357
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 18, 2011
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry
    Publication number: 20110233734
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: June 9, 2011
    Publication date: September 29, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: David H. Wells
  • Integrated Circuitry
    Publication number: 20110210400
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Application
    Filed: April 28, 2011
    Publication date: September 1, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Eric R. Blomiley
  • Electromagnetic radiation conduits
    Patent number: 8004055
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Methods of forming transistors
    Patent number: 7989322
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • EPITAXIAL SILICON GROWTH
    Publication number: 20110163354
    Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Du Li
  • Semiconductor structures including square cuts in single crystal silicon
    Patent number: 7973388
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
  • Integrated circuitry
    Patent number: 7956416
    Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Eric R. Blomiley