Patents by Inventor David M. Dobuzinsky
David M. Dobuzinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6208008Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.Type: GrantFiled: March 2, 1999Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: Kenneth C. Arndt, Richard A. Conti, David M. Dobuzinsky, Laertis Economikos, Jeffrey P. Gambino, Peter D. Hoh, Chandrasekhar Narayan
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Patent number: 6153474Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: July 1, 1998Date of Patent: November 28, 2000Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky, Jack Allan Mandelman, Mark Anthony Jaso
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Patent number: 6093281Abstract: A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.Type: GrantFiled: February 26, 1998Date of Patent: July 25, 2000Assignee: International Business Machines Corp.Inventors: Richard S. Wise, David M. Dobuzinsky, William C. Wille
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Patent number: 6066570Abstract: A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.Type: GrantFiled: December 10, 1998Date of Patent: May 23, 2000Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Dung-Ching Perng, David M. Dobuzinsky, Ting Hao Wang, Klaus Roithner
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Patent number: 5998100Abstract: A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.Type: GrantFiled: September 5, 1997Date of Patent: December 7, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tsukasa Azuma, Tokuhisa Ohiwa, Tetsuo Matsuda, David M. Dobuzinsky, Katsuya Okumura
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Patent number: 5939335Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.Type: GrantFiled: January 6, 1998Date of Patent: August 17, 1999Assignee: International Business Machines CorporationInventors: Kenneth C. Arndt, Richard A. Conti, David M. Dobuzinsky, Laertis Economikos, Jeffrey P. Gambino, Peter D. Hoh, Chandrasekhar Narayan
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Patent number: 5759746Abstract: A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.Type: GrantFiled: May 24, 1996Date of Patent: June 2, 1998Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corp.Inventors: Tsukasa Azuma, Tokuhisa Ohiwa, Tetsuo Matsuda, David M. Dobuzinsky, Katsuya Okumura
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5747866Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.Type: GrantFiled: January 21, 1997Date of Patent: May 5, 1998Assignee: Siemens AktiengesellschaftInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac -
Patent number: 5656535Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.Type: GrantFiled: March 4, 1996Date of Patent: August 12, 1997Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Herbert Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky, Jack A. Mandelman, Mark Anthony Jaso
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5643823Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.Type: GrantFiled: September 21, 1995Date of Patent: July 1, 1997Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, J. Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac -
Patent number: 5563105Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.Type: GrantFiled: September 30, 1994Date of Patent: October 8, 1996Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Tetsuo Matsuda, Son V. Nguyen, James G. Ryan, Michael Shapiro
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Patent number: 5539154Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.Type: GrantFiled: April 27, 1995Date of Patent: July 23, 1996Assignee: International Business Machines CorporationInventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
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Patent number: 5536360Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.Type: GrantFiled: January 3, 1995Date of Patent: July 16, 1996Assignee: International Business Machines CorporationInventors: Son V. Nguyen, David M. Dobuzinsky
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Patent number: 5468687Abstract: A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.Type: GrantFiled: July 27, 1994Date of Patent: November 21, 1995Assignee: International Business Machines CorporationInventors: Dan Carl, David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen
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Patent number: 5462812Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.Type: GrantFiled: December 29, 1992Date of Patent: October 31, 1995Inventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
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Patent number: 5455204Abstract: The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.Type: GrantFiled: December 12, 1994Date of Patent: October 3, 1995Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen
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Patent number: 5412246Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG..Type: GrantFiled: January 26, 1994Date of Patent: May 2, 1995Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, David L. Harmon, Srinandan R. Kasi, Donald M. Kenney, Son V. Nguyen, Tue Nguyen, Pai-Hung Pan
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Patent number: 5330935Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG..Type: GrantFiled: July 21, 1992Date of Patent: July 19, 1994Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, David L. Harmon, Srinandan R Kasi, Donald M. Kenney, Son Van Nguyen, Tue Nguyen, Pai-Hung Pan
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Patent number: 5217567Abstract: Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.Type: GrantFiled: February 27, 1992Date of Patent: June 8, 1993Assignee: International Business Machines CorporationInventors: Donna R. Cote, David M. Dobuzinsky, Son V. Nguyen
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Patent number: 5204138Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.Type: GrantFiled: December 24, 1991Date of Patent: April 20, 1993Assignee: International Business Machines CorporationInventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon