Abstract: A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data.

Abstract: A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.

Abstract: A number of data compression and decompression server processes and a socket interface to which these server processes can be attached are provided to each computer system of a network. Additionally, an OPEN, a WRITE, and a READ routine are provided to the operating system of each computer system of the network. The OPEN routine is used by a client sender process to establish connection to a client receiver process computer system. In the course of establishing the connection, the OPEN routine automatically negotiate a compression/decompression method between the sender and the receiver computer system. The WRITE routine is used by the client sender process to send data to the client process. In the course of sending the data, the WRITE routine automatically invokes the appropriate compression method to compress the data based on the result of the negotiation performed by the OPEN routine. The READ routine is used by the client receiver process to receive data from the sender process.

Abstract: A dynamic network configuration in a computer records and analyzes network transactions to permit dynamic configuration of network parameters when connecting the computer to a network. Upon initial connection of the computer to the network, user preferences and network parameters for other locations previously encountered are read or entered into memory of the computer. The dynamic network configuration gathers network traffic data by entering a learn or promiscuous mode to record a number of network transactions for a predetermined time period. The network traffic data is indexed for analysis to determine the participants. The current participants are compared with the existing participants for previously observed locations. If a match occurs, then the network parameters are utilized to configure a protocol stack.

Abstract: A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position.

Abstract: A food processing plant comprises a cooking kettle, a holding tank and a depositor. The holding tank is provided with wheels to permit the tank to be moved from a first position in the proximity of the cooking kettle to a second position in the proximity of the depositor. Means is provided for applying a vacuum to the tank in the first position to draw food product from the kettle through a first pipeline. Means is provided for applying pressurized air to the holding tank in the second position to expel the food product from the tank to the depositor. A cooling station is provided in the form of a booth into which the tank is movable after leaving the first position and before entering the second position. The booth includes frame means which supports a cooling unit movable from a raised position into a lowered position within the tank. The cooling unit includes rotary vanes with scrapers for contact with the wall of the tank. The cooling unit mounted on a cover adapted to rest on the rim of the tank.

Abstract: An information storage apparatus for first-in-first-out storage and output of information includes a plurality of storage cells, an input circuit for inputting information to the storage cells, and a control circuit for controlling the operation of the apparatus in response to at least one clock signal. The storage cells are arranged to effect serial progression of information therethrough in a predetermined sequence to an output, all in response to the control circuit. The control circuit directs the information through the input circuit to the empty cell of the plurality of storage cells which is most proximate to the output of the apparatus. The input circuit provides the information to a set of first storage cells and provides an inverse representation of the information to a set of second storage cells, the first storage cells preferably being odd-numbered storage cells from the output and the second storage cells preferably being even-numbered storage cells from the output.

Abstract: A propagating first-in, first-out (FIFO) storage device is driven by a two-phase non-overlapping clock and includes a plurality of storage cells (C1, . . . C4) and a plurality of tracking bit cell circuits (T1, . . . T4). Each of the storage cells includes first pass gate transistors (G1, . . . G8), first inverters (INV1, . . . INV8), second pass gate transistors (G9, . . . G16), and second inverters (INV9, . . . INV16). The first pass gate transistors are responsive to a control signal from the tracking circuit for loading data input signals into the first inverter means. The second pass gate transistors are responsive to a first phase of the clock for shifting the data input signals into the second inverters.