Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.

Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The first set of FETs has a first channel width. A second set of FETs of the plurality of FETs is coupled to a bitline complement of the memory array. The second set of FETs has a second channel width. The first channel width is greater than the second channel width. The channel width disparity provides the NVM element of the unprogrammed memory array with a default state.

Abstract: A circuit has a wordline with an NVM element utilizing a first FET coupled to bitline true and a second FET coupled to bitline complement. A NFET coupled to the bitline complement is configured to pull bitline true toward ground in response to bitline complement reaching a first voltage. One or more wordline drivers are coupled to the NVM element such that a first path from a wordline driver is coupled to the first FET while a second path from a wordline driver is coupled to the second FET. The first path is current-limited in comparison to the second path, such that a first slew rate between a wordline driver and the first FET is slower than a second slew rate between a wordline driver and the second FET. The slew rate disparity allows the bitline complement to reach the first voltage.

Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.

Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.

Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuity having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.

Abstract: A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on the substrate and positioned approximately parallel lengthwise to one another, a first gate layer and a second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The semiconductor structure can include an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The interconnect layer can be positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.

Abstract: An array of eFuses without a default state of logical one or logical zero includes rows and columns. One of the rows has data cells for programming as well as indicator data cells for indicating if the programmable data cells have been programmed. Each column includes a sense amplifier to sense the state of cells of the column. Sense amplifiers of columns with indicator data cells are coupled to one or more logic gates which determine if the indicator data cells are in a selected logical state. Sense amplifiers of columns with data cells are coupled to mask logic gates. The mask logic gates are coupled to both columns of data cells and outputs of the one or more logic gates. The logic gates mask outputs of the data cells when the indicator data cells are not in the selected logical state.

Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.

Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.

Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.

Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.

Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.