Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.

Abstract: A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on the substrate and positioned approximately parallel lengthwise to one another, a first gate layer and a second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The semiconductor structure can include an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The interconnect layer can be positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.

Abstract: A signaling bus having a plurality of adjacent logical lanes, each logical lane having an odd signal path and an even signal path. Driving circuitry drives each logical lane by transmitting, if data has changed from an immediately preceding cycle, a one cycle signal having a first transition direction on the even signal path on even cycles and transmitting a one cycle signal having the first transition direction on odd cycles. If data has not changed, transmitting a two cycle signal having a second transition direction on the even signal path on even cycles and transmitting a two cycle signal on the odd path having the second transition direction on odd cycles. Receiver circuitry alternates selection of the even cycle path and the odd cycle path to determine if data has changed from the immediately preceding cycle.

Abstract: A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a second plate of the capacitor is disclosed. The method may include forming the second plate of the capacitor by creating, in a top surface of the metal layer, the recess having at least one side and a bottom and depositing a conformal dielectric film onto the at least one side and the bottom of the recess. The method may also include forming the first plate of the capacitor by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the second plate.

Abstract: A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a second plate of the capacitor is disclosed. The method may include forming the second plate of the capacitor by creating, in a top surface of the metal layer, the recess having at least one side and a bottom and depositing a conformal dielectric film onto the at least one side and the bottom of the recess. The method may also include forming the first plate of the capacitor by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the second plate.

Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.

Abstract: A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.

Abstract: A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width.

Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on the substrate and positioned approximately parallel lengthwise to one another, a first gate layer and a second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The semiconductor structure can include an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The interconnect layer can be positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.

Abstract: A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width.

Abstract: A method of making a semiconductor device in a gate first process with side gate assists. A first gate may be formed within a gate region. The first gate may include a first gate conductor separated from a semiconductor substrate by a first insulator disposed between the first gate conductor and the semiconductor substrate. A second gate may be formed within the gate region. The second gate may include a second gate conductor separated from a vertical surface of the first gate conductor and the semiconductor substrate by a second insulator. A first electrical contact and a second electrical contact may be formed. The first and second electrical contacts may be disposed on opposite ends of the gate region for respectively connecting the first gate conductor and the second gate conductor to a respective voltage.

Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks.

Abstract: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.