Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method includes the steps of: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer, The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7?X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1?XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract: A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

Abstract: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

Abstract: Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

Abstract: A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a damascene trench over the bottom electrode; depositing a layer CMR material over the SiNx and in the damascene trench; removing the CMR material overlying the SiNx layer by CMP, leaving the CMR material in the damascene trench; and completing the CMOS structure.

Abstract: An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.

Abstract: A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H2O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.

Abstract: A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

Abstract: A method of forming a tungsten nitride thin film in an integrated circuit includes preparing a silicon substrate on a silicon wafer and placing the silicon wafer in a heatable chuck in a CVD vacuum chamber; placing a known quantity of a tungsten source in a variable-temperature bubbler to provide a gaseous tungsten source; setting the variable-temperature bubbler to a predetermined temperature; passing a carrier gas through the variable-temperature bubbler and carrying the gaseous tungsten source with the carrier gas into the CVD vacuum chamber; introducing a nitrogen-containing reactant gas into the CVD vacuum chamber; reacting the gaseous tungsten source and the nitrogen-containing reactant gas above the surface of the silicon wafer in a deposition process to deposit a WxNy thin film on the surface of the silicon wafer; and completing the integrated circuit containing the WxNy thin film.

Abstract: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1?xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2?(3±20%); Mn3+((1?x)±20%); and, Mn4+(x±20%). When the PCMO thin film has a Pr3+0.70Ca2+0.30Mn3+0.78Mn4+0.22O2?2.96 composition, the ratio of Mn and O ions varies as follows: O2?(2.96); Mn3+((1?x)+8%); and, Mn4+(x?8%). In another aspect, the method creates a density in the PCMO film, responsive to the crystallographic orientation. For example, if the PCMO film has a (110) orientation, a density is created in the range of 5 to 6.76 Mn atoms per 100 ?2 in a plane perpendicular to the (110) orientation.

Abstract: A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract: A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array.

Abstract: Perovskite materials having magnetoresistive effect under the influence of an electric field can be employed in the construction of nonvolatile solid state electro-optic modulator. These materials display nonvolatile changes in electrical resistance and reactant when subjected to an electric field. As with other known perovskite materials, this is accompanied by nonvolatile changes in electro-optic properties related to dispersion and absorption of electromagnetic radiation. The nonvolatility of these materials is exploited in the construction of nonvolatile display and nonvolatile solid state electro-optic modulators such as waveguide switch or phase or amplitude modulators.

Abstract: A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Abstract: A method of fabricating a PCMO thin film at low temperature for use in a RRAM device includes preparing a PCMO precursor; preparing a substrate; placing the substrate into a MOCVD chamber; introducing the PCMO precursor into the MOCVD chamber to deposit a PCMO thin film on the substrate; maintaining a MOCVD vaporizer at between about 240° C. to 280° C. and maintaining the MOCVD chamber at a temperature of between about 300° C. to 400° C.; removing the PCMO thin-film bearing substrate from the MOCVD chamber; and completing the RRAM device.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.