Abstract: A Cu(hfac) precursor with a substituted phenylethylene ligand has been provided. The substituted phenylethylene ligand includes bonds to molecules selected from the group consisting of C1 to C6 alkyl, C1 to C6 haloalkyl, C1 to C6 phenyl, H and C1 to C6 alkoxyl. One variation, the &agr;-methylstyrene ligand precursor has proved to be stable a low temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursor.

Abstract: A method of forming a titanium-based barrier metal layer includes preparing a substrate, including forming IC elements on the substrate; forming a titanium-based barrier metal precursor using a solution of about 5% by volume tetrakis (methylethylamino) titanium (TMEAT) and about 95% by volume octane; and depositing a titanium-based barrier layer on the substrate by MOCVD.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure.

Abstract: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

Abstract: A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.

Abstract: A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.

Abstract: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

Abstract: A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

Abstract: A fabrication process provides for achieving high adhesion of CVD copper thin films on metal nitride substrates, and in particular, on substrates having an outermost TaN layer. The method comprises introducing a certain amount of water vapor to the initial copper thin film deposition stage and reducing the amount of fluorine in the interface of the copper and metal nitride substrate. These two process steps result in a copper thin film having improved adhesion to metal nitride substrates, including TaN substrates.

Abstract: A method of forming a copper thin film by chemical vapor deposition, includes introducing a wafer into a chemical vapor deposition chamber; humidifying helium gas with water to form a wet helium gas for use as the atmosphere in the chemical vapor deposition chamber; depositing a copper seed layer at a wet helium flow rate of between about 5.0 sccm and 20.0 sccm during a wafer temperature rise from ambient temperature to between about 150° C. to 230° C.; and depositing a copper thin film layer at a wet helium flow rate of between about 0.2 sccm to 1.0 sccm and at a temperature of between about 150° C. to 230° C.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

Abstract: A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided The method removes metal oxides with &bgr;-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed.

Abstract: A method of chemical vapor deposition (CVD) of copper films includes preparing a substrate, including forming structures thereon have a barrier metal exposed surface; placing the prepared substrate into a CVD chamber; heating the substrate to a temperature of between about 200° C. and 250° C.; introducing a water flow in a carrier gas for at least one minute; stopping the water flow; and starting the flow of copper precursor.

Abstract: A method of shallow trench isolation includes preparing a substrate, including forming mesa structures thereon; forming a barrier cap on the mesa structures; forming an oxide multi-layer structure over the mesas and barrier caps, including: depositing a first oxide layer having a conventional polishing rate; depositing a second oxide layer having a low polishing rate; and depositing a third oxide layer having a conventional polishing rate, and polishing the structure to the level of the barrier cap.

Abstract: A method of forming a copper thin film on an integrated circuit substrate having a nitride component includes preparing the substrate; treating the substrate prior to copper deposition; depositing copper during a very short duration copper deposition step lasting between about ten seconds to 40 seconds; baking the substrate and the deposited copper for between about one minute to ten minutes at a temperature greater than 385° C.; and depositing copper during a long duration copper deposition step to deposit copper to the required thickness.

Abstract: A method of shallow trench isolation includes preparing a substrate, including forming mesa structures thereon; forming a barrier cap on the mesa structures; forming an oxide multi-layer structure over the mesas and barrier caps, including: depositing a first oxide layer having a conventional polishing rate; depositing a second oxide layer having a low polishing rate; and depositing a third oxide layer having a conventional polishing rate; and polishing the structure to the level of the barrier cap.

Abstract: A method of forming a copper thin film by chemical vapor deposition, includes introducing a wafer into a chemical vapor deposition chamber; humidifying helium gas with water to form a wet helium gas for use as the atmosphere in the chemical vapor deposition chamber; depositing a copper seed layer at a wet helium flow rate of between about 5.0 sccm and 20.0 sccm during a wafer temperature rise from ambient temperature to between about 150° C. to 230° C.; and depositing a copper thin film layer at a wet helium flow rate of between about 0.2 sccm to 1.0 sccm and at a temperature of between about 150° C. to 230° C.

Abstract: The present invention provides a method of fabricating a simple SiGe/SOI structure. In particular, the top silicon layer of a SOI is converted to Si1−xGex, by growing a SiGe epitaxial layer followed by relaxation annealing at a temperature between 550° C. to 1050° C. This temperature treatment relaxes the SiGe to convert the top silicon layer into a relaxed SiGe layer and eliminates defects in the SOI film. Accordingly, a very low defect density SiGe crystal is obtainable. The SiGe layer is capped with an epitaxial silicon layer. Because the silicon layer is grown onto the relaxed SiGe, the top silicon layer is a strained silicon layer. Therefore, higher electron and hole mobility are obtained. The buried oxide interface acts as a buffer for the SiGe relaxation. There is no requirement for a graded SiGe layer. As a result the defect density in this structure can be substantially lower than that of prior art structures.