Abstract: Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.

Abstract: Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing a memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.

Abstract: Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.

Abstract: Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.

Abstract: Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed.

Abstract: Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.

Abstract: Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the first memory unit.

Abstract: A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is configured to sense and compare a reference voltage and an operating voltage. In one or more embodiments the voltage sensor is also configured to generate an alarm signal if the difference between the operating voltage and the reference voltage indicates the operating voltage is outside of a normal operating range.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.

Abstract: Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a source configured to communicate signals to a memory device. At least one memory cube may coupled to the source by a communications link having more than one communications path. The memory cube may include a memory device operably coupled to a routing switch that selectively communicates the signals between the source and the memory device.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.