Abstract: Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing the memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.

Abstract: Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is configured to sense and compare a reference voltage and an operating voltage. In one or more embodiments we voltage sensor is also configured to generate an alarm signal if the difference between the operating voltage and the reference voltage indicates the operating voltage is outside of a normal operating range.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A memory module comprises a plurality of storage bits for each memory location, and a plurality of error management storage bits for each memory location. A memory controller is operable to change error management modes on the memory module. Changing error management modes comprises in one example using an error management mode providing the greatest error management capability for the number of operable memory components available within the memory module.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation.

Abstract: A process in memory chip has been designed to combine memory and computation on the same integrated circuit in a way that makes use of the bandwidth that results from the combination. The chip contains multiple single-bit computational processors that are all driven in parallel. Error correction logic is also incorporated into the chip to detect and correct errors in memory, data as they occur.

Abstract: A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices.

Abstract: An improved built-in self-test system fabricated on an LSI circuit chip for performing dynamic tests of main logic function operation. The built-in self-test system includes a control register comprising a series of static flip-flops connected for serial test data transfer and for producing test system control signals. An input shift register connected for serial test data transfer with the control register and for parallel test data transfer with the main logic function is formed by a series arrangement of static flip-flops. An output register connected for serial test data transfer with the input register, and for parallel test data transfer with the main logic function, is formed by a series arrangement of static flip-flops. A test clock enable signal is latched by a test clock enable latch, and gated with a system clock signal to produce input and output register clock signals. A test strobe signal is latched by a test strobe latch and strobed by a flip-flop for use as a control register enable signal.

Abstract: A microcode program sequencer includes first and second registers (herein designated the Q and P registers), each connected to a computer memory to receive addresses therefrom. Control means is provided for each register such that the P register will provide output addresses to a microcode memory, whereas the Q register(s) provide output addresses to the P register. By properly operating the control means, incrementing of addresses from the P register can be accomplished, as well as address jumps and returns, using the Q register. Further, the contents of the Q register may also be incremented in synchronism with the P register, as desired. One feature of the invention resides in a conditional latch circuit which may be selectively operated as a latch or as an OR gate.

Abstract: A conditional latch circuit is selectively operable as a latch or as an OR gate. The circuit comprises an OR gate having at least three inputs, each connected to the output of separate ones of three AND gates. A fourth AND gate has an inverted output connected to an input of two AND gates and a non-inverted output connected to an input of the third AND gate. The output of the OR gate is connected to a second input of the third AND gate. With one input of the fourth AND gate connected to a binary clock source, the circuit will operate as a latch to store binary signals received at the second input of the first and second AND gates when the second input of the fourth AND gate is connected to binary one. When the second input of the fourth AND gate is connected to a binary zero, the circuit will operate as an OR circuit.