Abstract: Provided herein are sample collection devices that include a first body structure portion that comprises a drying agent compartment configured to receive a drying agent and a second body structure portion operably connected, or connectable, to the first body structure portion. The second body structure portion includes a sample collection support compartment comprising one or more segments that communicate with the drying agent compartment at least when the first and second body structure portions are operably connected to one another in a closed position. The sample collection support compartment is configured to receive a sample collection support. Related kits, systems, computer readable media, and methods are also provided.

Abstract: Circuit breakers with a housing with a line side and a load side and an electronically controlled lock-out lock member coupled to the housing configured to electronically controllably travel between a first position and a second position. In the second position, the lock member is in a lock-out position and prevents the handle from moving to an ON position associated with electrical current conduction and in the first position the lock member is translated to a position that allows the handle to move to the ON position.

Abstract: A work station including a base includes a work surface pivotally mounted to the base so as to be configured to pivot between a first position and a second position. The work surface is configured to cover a protected member when in a first position and the work surface is configured to uncover the protected member when moved into a second position. The base is configured to support the work surface on a floor surface. A height of the work surface can be adjusted to accommodate the ergonomic needs of different users.

Abstract: A microelectromechanical system (MEMS) resonator includes a resonant semiconductor structure, drive electrode, sense electrode and electrically conductive shielding structure. The first drive electrode generates a time-varying electrostatic force that causes the resonant semiconductor structure to resonate mechanically, and the first sense electrode generates a timing signal in response to the mechanical resonance of the resonant semiconductor structure. The electrically conductive shielding structure is disposed between the first drive electrode and the first sense electrode to shield the first sense electrode from electric field lines emanating from the first drive electrode.

Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

Abstract: An apparatus and method are provided for performing an index operation. The apparatus has vector processing circuitry to perform an index operation in each of a plurality of lanes of parallel processing. The index operation requires an index value opm to be multiplied by a multiplier value e to produce a multiplication result. The number of lanes of parallel processing is dependent on a specified element size, and the multiplier value is different, but known, for each lane of parallel processing. The vector processing circuitry comprises mapping circuitry to perform, within each lane, mapping operations on the index value opm in order to generate a plurality of intermediate input values. The plurality of intermediate input values are such that the addition of the plurality of intermediate input values produces the multiplication result. Within each lane the mapping operations are determined by the multiplier value used for that lane.

Abstract: An apparatus has floating-point multiplying circuitry to perform a floating-point multiply operation to multiply first and second floating-point operands to generate a product floating-point value. Shared hardware circuitry of the floating-point multiplying circuitry is reused to also support a floating-point scaling instruction specifying an input floating-point operand and an integer operand, which causes a floating-point scaling operation to be performed to generate an output floating-point value corresponding to a product of the input floating-point operand and a scaling factor 2X, where X is an integer represented by the integer operand.

Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.

Abstract: A floating-point adding circuitry is provided to add first and second floating-point operands each comprising a significand and an exponent. Alignment shift circuitry shifts a smaller-operand significand to align with a larger-operand significand, based on an exponent difference. Incrementing circuitry generates alternative versions of the larger-operand significand, each version based on a different rounding increment applied to the larger-operand significand. A number of candidate sum values are generated by adding circuits, each candidate sum value representing a sum of the shifted smaller-operand significand and a respective one of the alternative versions of the larger-operand significand. One of the candidate sum values is selected as a rounded result of adding the first and second floating-point operands. This allows floating-point addition to be performed faster as the latency of the rounding increment can be hidden in the shadow of the latency of the alignment shift.

Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

Abstract: Various implementations described herein are directed to providing time-dependent authentication of a sending device. A message to a designated receiver is prepared. A portion of at least one secret identifier value of the sending device is retrieved. A portion of time information is retrieved. An authentication field is produced using the portion of the at least one secret identifier value and the portion of the time information. The authentication field is attached to the message. The message is transmitted to the designated receiver.

Abstract: A feeding tube position confirmation device 102, operable to confirm the position of a predetermined portion of a medical feeding tube in a predetermined portion of a human or animal body, the position confirmation device comprising an optical waveguide 106 dimensioned to be insertable into the lumen of the feeding tube, the optical waveguide having a sensing distal end 108 comprising a distal end material and a sensing material mixed with the distal end material, the sensing material operable to provide a change in optical properties at the distal end 110 of the optical waveguide dependent on the environment to which the sensing distal end 108 of the waveguide is exposed. The sensing material may comprise a reflective material. Methods of manufacture and use of such devices are also described.

Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.

Abstract: A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. The intermediate value includes a number of leading 0s indicative of a prediction of a number of leading 0s in a difference between absolute values of the first floating point number and the second floating point number. The prediction differs by at most one from the number of leading 0s in the difference between absolute values of the first floating point number and the second floating point number. Count circuitry counts the number of leading 0s in said intermediate value and mask generation circuitry produces one or more masks using the intermediate value. The mask generation circuitry produces the one or more masks at the same time or before the count circuitry counts the number of leading 0s in the intermediate value.

Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.

Abstract: Processing circuitry is provided for comparing a number of adjacent widths having a common value and extending from a starting position within an input number with a runlength specified by a variable number. The circuitry includes a mask generator for generating a mask value in dependence upon the variable number, combination circuitry for performing a logical combination operation upon respective bits within the input number starting from the starting position and corresponding bits within the mask value so as to generate an intermediate value. Result circuitry then generates a result indicative of whether or not the number of adjacent bits is less than or equal to the run length in dependence upon a determination if any bits within the intermediate value have a predetermined value.

Abstract: The present invention relates to therapeutic dosing regimens utilizing a dose reduction strategy for treating disorders characterized by marked elevations of low density protein cholesterol (LDL-C) in the plasma of a patient. The subject therapeutic dosing regimens involve delivering as a single administration or plurality of administrations of an anti-proprotein convertase subtilisin kexin type 9 (PCSK9) antagonist antibody as an initial dose of at least about 100 mg, and delivering as a single administration or plurality of administrations at a subsequent dose in an amount that is about the same as the initial dose, or at least half the initial dose after the patient has a LDL-C level at or below about 25, 20, 15 or 10 mg/dL, preferably at or below 10 mg/dL.