Abstract: An apparatus comprises: processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored-data processing operation to generate an anchored-data element. The anchored-data element has an encoding including type information indicative of whether the anchored-data element represents: a portion of bits of a two's complement number, said portion of bits corresponding to a given range of significance representable using the anchored-data element; or a special value other than said portion of bits of a two's complement number.

Abstract: A microelectromechanical system (MEMS) resonator includes a resonant semiconductor structure, drive electrode, sense electrode and electrically conductive shielding structure. The first drive electrode generates a time-varying electrostatic force that causes the resonant semiconductor structure to resonate mechanically, and the first sense electrode generates a timing signal in response to the mechanical resonance of the resonant semiconductor structure. The electrically conductive shielding structure is disposed between the first drive electrode and the first sense electrode to shield the first sense electrode from electric field lines emanating from the first drive electrode.

Abstract: An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1<E<J?L and 1<F<K?M. In response to the MAP instruction, the instruction decoder controls the processing circuitry to rearrange F-bit portions of the second K-bit operand to form a transformed K-bit operand, and to control the L×M multiplier array in dependence on the first J-bit operand and the transformed K-bit operand to add the respective E×F products using a subset of the adders used for accumulating partial products for a conventional multiplication.

Abstract: A feeding tube position confirmation device 102, operable to confirm the position of a predetermined portion of a medical feeding tube in a predetermined portion of a human or animal body, the position confirmation device comprising an optical waveguide 106 dimensioned to be insertable into the lumen of the feeding tube, the optical waveguide having a sensing distal end 108 comprising a distal end material and a sensing material mixed with the distal end material, the sensing material operable to provide a change in optical properties at the distal end 110 of the optical waveguide dependent on the environment to which the sensing distal end 108 of the waveguide is exposed. The sensing material may comprise a reflective material. Methods of manufacture and use of such devices are also described.

Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

Abstract: A data processing apparatus includes difference circuitry that calculates a difference between exponents of a first floating-point operand and a second floating-point operand. Shift circuitry generates a fractional string by shifting fractional bits of a selected operand of the first floating-point operand and the second floating-point operand based on the difference. Logic circuitry generates an integer-bit string representing an integer-bit of the selected operand having been shifted based on the difference. Combining circuitry combines the fractional string and the integer-bit string to produce a significand string representing the selected operand having been shifted based on the difference. The logic circuitry generates the integer-bit string using operations other than shifting.

Abstract: A data processing apparatus and method of operating a data processing apparatus are disclosed. Comparisons are made between first and second floating-point operands received. A more significant portion of the first floating-point operand and of the second floating-point operand are subject to comparison. The more significant portion of the first floating-point operand minus a least significant bit in the more significant portion is subject to comparison with the more significant portion of the second floating-point operand. A less significant portion of the first floating-point operand and of the second floating-point operand are also subject to comparison. In dependence on the outcome of these comparisons, right-shift circuitry is used selectively to perform a 1-bit right shift on a difference calculated between the first floating-point operand and the second floating-point operand.

Abstract: A data processing system includes instruction decoder circuitry responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry performs a right shift upon at least part of the input number and left shifting circuitry performs a left shift of at least part of the input number. Selection circuitry serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.

Abstract: A feeding tube position confirmation device 102, operable to confirm the position of a predetermined portion of a medical feeding tube in a predetermined portion of a human or animal body, the position confirmation device comprising an optical waveguide 106 dimensioned to be insertable into the lumen of the feeding tube, the optical waveguide having a sensing distal end 108 comprising a distal end material and a sensing material mixed with the distal end material, the sensing material operable to provide a change in optical properties at the distal end 110 of the optical waveguide dependent on the environment to which the sensing distal end 108 of the waveguide is exposed. The sensing material may comprise a reflective material. Methods of manufacture and use of such devices are also described.

Abstract: A data processing apparatus and method of operating a data processing apparatus are disclosed. Comparisons are made between first and second floating-point operands received. A more significant portion of the first floating-point operand and of the second floating-point operand are subject to comparison. The more significant portion of the first floating-point operand minus a least significant bit in the more significant portion is subject to comparison with the more significant portion of the second floating-point operand. A less significant portion of the first floating-point operand and of the second floating-point operand are also subject to comparison. In dependence on the outcome of these comparisons, right-shift circuitry is used selectively to perform a 1-bit right shift on a difference calculated between the first floating-point operand and the second floating-point operand.

Abstract: An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted.

Abstract: An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted.

Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.

Abstract: A frame module for a circuit breaker includes a first interface structured to connect to a trip unit, a second interface structured to connect to a frame, and a current rating storage unit structured to store a current rating associated with the frame and to provide the stored current rating to the trip unit when the trip unit is connected to the first interface.

Abstract: An apparatus and method are provided for estimating a shift amount when employing processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value. Shift estimation circuitry then determines an estimated shift amount to be applied to the difference value. The shift estimation circuitry comprises significand analysis circuitry to generate, from analysis of the significand values of the two floating-point operands, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value. In parallel, shift limiting circuitry generates from an exponent value a second bit string identifying a shift limit bit position.

Abstract: A data processing apparatus includes difference circuitry that calculates a difference between exponents of a first floating-point operand and a second floating-point operand. Shift circuitry generates a fractional string by shifting fractional bits of a selected operand of the first floating-point operand and the second floating-point operand based on the difference. Logic circuitry generates an integer-bit string representing an integer-bit of the selected operand having been shifted based on the difference. Combining circuitry combines the fractional string and the integer-bit string to produce a significand string representing the selected operand having been shifted based on the difference. The logic circuitry generates the integer-bit string using operations other than shifting.

Abstract: An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1<E<J?L and 1<F<K?M. In response to the MAP instruction, the instruction decoder controls the processing circuitry to rearrange F-bit portions of the second K-bit operand to form a transformed K-bit operand, and to control the L×M multiplier array in dependence on the first J-bit operand and the transformed K-bit operand to add the respective E×F products using a subset of the adders used for accumulating partial products for a conventional multiplication.

Abstract: In one embodiment, a method, system, and apparatus is for storing an assigned operations, administration and management (OAM) bitstring in a memory in a BIER (Bit Index Explicit Replication) enabled router, the OAM bitstring being assigned to a BIER domain, the semantic of the OAM bitstring being to replicate and forward the OAM bitstring to neighboring bit-forwarding routers (BFRs), generating an OAM probe packet including the OAM bitstring, setting a BFR ID associated with a first BFR as a BIER header bitstring in the OAM probe packet, setting a TTL (time to live) field in the OAM probe packet to be 2, sending the OAM probe packet to a next hop BFR, and performing one of receiving the OAM probe packet back from the first BFR, and taking an alternative action if the OAM probe packet is not received back from the first BFR.

Abstract: An apparatus and method are provided for estimating a shift amount when employing processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value. Shift estimation circuitry then determines an estimated shift amount to be applied to the difference value. The shift estimation circuitry comprises significand analysis circuitry to generate, from analysis of the significand values of the two floating-point operands, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value. In parallel, shift limiting circuitry generates from an exponent value a second bit string identifying a shift limit bit position.

Abstract: A floating point adder includes leading zero anticipation circuitry to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry.