Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.

Abstract: A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. A first shifter 28 shifts input signals representing the fixed point number by a first shift amount depending upon a leading zero count within an integer portion followed by a fractional portion of the fixed point number. A second shifter 30 shifts the input signals by a second shift amount depending upon the variable point position within the fixed point number. A subnormal result detector 34 generates a selection signal in dependence upon detection of a combination of a variable point position and the count of leading zeros which corresponds to the floating point number having a subnormal value. Selection circuitry 32 selects one of the outputs from the first shifter or the second shifter to form the significand in dependence upon the selection signal generated by the subnormal result detector.

Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

Abstract: A microelectromechanical system (MEMS) resonator includes a resonant semiconductor structure, drive electrode, sense electrode and electrically conductive shielding structure. The first drive electrode generates a time-varying electrostatic force that causes the resonant semiconductor structure to resonate mechanically, and the first sense electrode generates a timing signal in response to the mechanical resonance of the resonant semiconductor structure. The electrically conductive shielding structure is disposed between the first drive electrode and the first sense electrode to shield the first sense electrode from electric field lines emanating from the first drive electrode.

Abstract: A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. The intermediate value includes a number of leading 0s indicative of a prediction of a number of leading 0s in a difference between absolute values of the first floating point number and the second floating point number. The prediction differs by at most one from the number of leading 0s in the difference between absolute values of the first floating point number and the second floating point number. Count circuitry counts the number of leading 0s in said intermediate value and mask generation circuitry produces one or more masks using the intermediate value. The mask generation circuitry produces the one or more masks at the same time or before the count circuitry counts the number of leading 0s in the intermediate value.

Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding such a convert and accumulate instruction within the sequence of instructions to generate one or more control signals to control the execution circuitry. In particular, the execution circuitry is responsive to such control signals to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand.

Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

Abstract: Computer program instruction oriented data processor logic cell that independently determines when its instruction should be processed, data processors made of the aforementioned logic cells, networks made of the aforementioned data processors, and methods of operating the aforementioned.

Abstract: A golf club (2) comprising a shaft (20), a head and a damping device (1, 100). The damping device (1, 100) includes an anchor element (3, 103) and a damping element (4, 104) interconnected by a rigid rod (5, 105). The anchor element (3, 103) is anchored within the lower section of the shaft (20) that has a substantially constant diameter such that the damping element (4, 104) is in contact with an internal surface of the shaft (20) to dampen vibrations therein.

Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.

Abstract: An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.

Abstract: A floating point adder includes leading zero anticipation circuitry 18 to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry 40.

Abstract: A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. A first shifter 28 shifts input signals representing the fixed point number by a first shift amount depending upon a leading zero count within an integer portion followed by a fractional portion of the fixed point number. A second shifter 30 shifts the input signals by a second shift amount depending upon the variable point position within the fixed point number. A subnormal result detector 34 generates a selection signal in dependence upon detection of a combination of a variable point position and the count of leading zeros which corresponds to the floating point number having a subnormal value. Selection circuitry 32 selects one of the outputs from the first shifter or the second shifter to form the significand in dependence upon the selection signal generated by the subnormal result detector.

Abstract: A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Abstract: A circuit protection apparatus includes separable contacts, an operating mechanism, an electronic trip unit storing a plurality of trip parameter combinations, wherein each of the trip parameter combinations specifies a certain value for each of a plurality of individual trip parameters, and a multi-position selector moveable among a plurality of predetermined positions and configured to enable selection of one of the predetermined positions. Each of the positions corresponds to a respective one of the trip parameter combinations, wherein the electronic trip unit is structured to, responsive to a chosen one of the plurality of predetermined positions being selected by the multi-position selector, cause the one of the trip parameter combinations corresponding to the chosen one of the plurality of predetermined positions to be used by the electronic trip unit to determine whether to cause the operating mechanism to trip open the separable contacts.

Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

Abstract: An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.

Abstract: An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands. An unbiased result exponent is determined from operand exponent values and leading zero counts, and a shift amount and direction for a product significand as needed for a predetermined minimum exponent value of a predetermined canonical format. First and second rounding values for injection into addition of the partial products are generated by shifting a predetermined rounding pattern by the shift amount in an opposite shift direction for the first rounding value and left shifting by one bit the first rounding value to give the second. The first and second partial products are added together with the first rounding value to give a first product significand, and are added together with the second rounding value to give a second product significand.

Abstract: A data processing system supports execution of program instructions having a rounding position input operand so as to generate control signals for controlling processing circuitry to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.

Abstract: The present invention relates to therapeutic dosing regimens utilizing a dose reduction strategy for treating disorders characterized by marked elevations of low density protein cholesterol (LDL-C) in the plasma of a patient. The subject therapeutic dosing regimens involve delivering as a single administration or plurality of administrations of an anti-proprotein convertase subtilisin kexin type 9 (PCSK9) antagonist antibody as an initial dose of at least about 100 mg, and delivering as a single administration or plurality of administrations at a subsequent dose in an amount that is about the same as the initial dose, or at least half the initial dose after the patient has a LDL-C level at or below about 25, 20, 15 or 10 mg/dL, preferably at or below 10 mg/dL.