Patents by Inventor Davood Shahrjerdi

Davood Shahrjerdi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE
    Publication number: 20160316539
    Abstract: Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
    Type: Application
    Filed: November 1, 2015
    Publication date: October 27, 2016
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Breakdown voltage multiplying integration scheme
    Patent number: 9478651
    Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE
    Publication number: 20160307892
    Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 20, 2016
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Flexible active matrix circuits for interfacing with biological tissue
    Patent number: 9472631
    Abstract: High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Active matrix using hybrid integrated circuit and bipolar transistor
    Patent number: 9472607
    Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • Monolithic integration of heterojunction solar cells
    Patent number: 9472703
    Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE
    Publication number: 20160300956
    Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 13, 2016
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Flexible active matrix display
    Patent number: 9466651
    Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen W. Bedell, III, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • HETEROSTRUCTURE GERMANIUM TANDEM JUNCTION SOLAR CELL
    Publication number: 20160284926
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Application
    Filed: June 10, 2016
    Publication date: September 29, 2016
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER
    Publication number: 20160284916
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Application
    Filed: June 10, 2016
    Publication date: September 29, 2016
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Silicon-containing, tunneling field-effect transistor including III-N source
    Patent number: 9425312
    Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Artificial electronic skin
    Patent number: 9421087
    Abstract: High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Passivation of back-illuminated image sensor
    Patent number: 9406717
    Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • FABRICATION OF III-V-ON-INSULATOR PLATFORMS FOR SEMICONDUCTOR DEVICES
    Publication number: 20160211170
    Abstract: Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • Semiconductor structure with an L-shaped bottom plate
    Patent number: 9397094
    Abstract: A semiconductor structure having a first source/drain semiconductor structure connected to a vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel, the vertical channel being perpendicular relative to a layer of substrate to which the source/drain semiconductor structure is attached.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Monolithic integration of heterojunction solar cells
    Patent number: 9397246
    Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Heterojunction bipolar transistors with intrinsic interlayers
    Patent number: 9391180
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • FABRICATION OF III-V-ON-INSULATOR PLATFORMS FOR SEMICONDUCTOR DEVICES
    Publication number: 20160196972
    Abstract: Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • NANOFLUID SENSOR WITH REAL-TIME SPATIAL SENSING
    Publication number: 20160187288
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Application
    Filed: December 31, 2014
    Publication date: June 30, 2016
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Silicon heterojunction photovoltaic device with wide band gap emitter
    Patent number: 9373743
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi