Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.

Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.

Abstract: Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.

Abstract: An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1?x passivated by amorphous SiyGe1?y:H.

Abstract: A reactive material stack is formed above a surface of a base substrate. The reactive material stack includes metals which when subjected to heat energy or electrical energy can undergo a solid state reaction that provides an intermetallic compound. The intermetallic compound that forms has a smaller unit volume than the initial reactive material stack and, as such, induces a tensile stress within the base substrate which, in turn, initiates crack formation within the base substrate. This represents an initial stage of spalling. The crack formation can be propagated along a fracture plane within the base substrate by continued spalling.

Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.

Abstract: Semiconductor devices having vertical field effect transistors with self-aligned source and drain contacts are provided, as well as methods for fabricating vertical field effect transistors with self-aligned source and drain contacts.

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: A semiconductor structure having a first source/drain semiconductor structure connected to a vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel, the vertical channel being perpendicular relative to a layer of substrate to which the source/drain semiconductor structure is attached.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: A solar cell includes a p-type semiconductor substrate including a plurality of thin absorption regions and a plurality of thick absorption regions. The plurality of thin absorption regions and the plurality of thick absorption regions are coplanar on a bottom side thereof. An n-type semiconductor layer is disposed over a top side of the p-type semiconductor substrate. The n-type semiconductor layer has a substantially uniform thickness. Metallurgy is disposed on top of the n-type semiconductor layer. The plurality of thin absorption regions are sufficiently thin to render the semiconductor substrate flexible.

Abstract: A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array.

Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.

Abstract: A pixel circuit for an active matrix organic light-emitting diode display system includes a first input node, a second input node, first power supply node, a second power supply node, a triode switch circuit, a storage capacitor, an organic light emitting diode, and a resistive element. The triode switch circuit is connected to the first and second input nodes. The storage capacitor is connected between an output of the triode switch circuit and the second power supply node. The organic light-emitting diode is connected between the output of the triode switch circuit and the second power supply node. The first resistive element is connected between the output of the triode switch circuit and the first power supply node.