Patents by Inventor Davood Shahrjerdi

Davood Shahrjerdi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS
    Publication number: 20170279000
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Application
    Filed: June 14, 2017
    Publication date: September 28, 2017
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Silicon-containing, tunneling field-effect transistor including III-N source
    Patent number: 9773909
    Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Switched-capacitor biosensor device
    Patent number: 9746442
    Abstract: A sensing apparatus includes a device containing microwells and a switched capacitor circuit in which at least one of the sensing/storage capacitors is a capacitor that extends perpendicularly with respect to a semiconductor device layer containing field effect transistors. Capacitor structures extend into microwells or within a doped layer on a handle substrate. Ion generation within the microwells is sensed using the circuit.
    Type: Grant
    Filed: March 30, 2014
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Thin light emitting diode and fabrication method
    Patent number: 9741897
    Abstract: A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Contact for silicon heterojunction solar cells
    Patent number: 9741889
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Nanofluid sensor with real-time spatial sensing
    Patent number: 9733210
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Silicon heterojunction photovoltaic device with wide band gap emitter
    Patent number: 9716201
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • MONOLITHIC INTEGRATION OF III-V CELLS FOR POWERING MEMORY ERASURE DEVICES
    Publication number: 20170200684
    Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventors: Kenneth Rodbell, Davood Shahrjerdi
  • Fabrication of III-V-on-insulator platforms for semiconductor devices
    Patent number: 9698046
    Abstract: Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • III-V solar cell structure with multi-layer back surface field
    Patent number: 9680045
    Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Solar cell structures having III-V base layers
    Patent number: 9666742
    Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1-x passivated by amorphous SiyGe1-y:H.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Semiconductor on insulator substrate with back bias
    Patent number: 9666615
    Abstract: A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Interdigitated back contact heterojunction photovoltaic device
    Patent number: 9640699
    Abstract: A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 2, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH BACK BIAS
    Publication number: 20170110491
    Abstract: A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION
    Publication number: 20170081781
    Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
    Type: Application
    Filed: December 7, 2016
    Publication date: March 23, 2017
    Inventors: BAHMAN HEKMATSHOAR-TABARI, ALI KHAKIFIROOZ, ALEXANDER REZNICEK, DEVENDRA K. SADANA, GHAVAM G. SHAHIDI, DAVOOD SHAHRJERDI
  • HYBRID BIPOLAR JUNCTION TRANSISTOR
    Publication number: 20170077185
    Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
    Type: Application
    Filed: November 27, 2016
    Publication date: March 16, 2017
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Tak H. Ning, Davood Shahrjerdi
  • HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE
    Publication number: 20170069689
    Abstract: Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
    Type: Application
    Filed: November 20, 2016
    Publication date: March 9, 2017
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Back-end transistors with highly doped low-temperature contacts
    Patent number: 9577065
    Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wilfried E. Haensch, Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE
    Publication number: 20170047378
    Abstract: Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 16, 2017
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD
    Publication number: 20170047467
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi