Abstract: A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure.

Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.

Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.

Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.

Abstract: Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of SixGe1?x passivated by amorphous SiyGe1?y:H.

Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.

Abstract: An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.

Abstract: A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer.

Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.

Abstract: A system for disinfecting a water sample includes a pipe having an inlet for engaging a source of the water sample, a storage reservoir connected to an outlet of the pipe for holding the water sample, an array of photovoltaic cells coupled to the pipe for converting solar radiation into a current, and an array of light emitting diodes coupled to the pipe and powered by the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation. A method for disinfecting a fluent water sample includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the fluent water sample to the radiation while transporting the fluent water sample from a source to a storage reservoir.

Abstract: Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing.

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: High resolution active matrix nanowire circuits enable a flexible and stretchable platform for probing neural circuits. Fabrication of such circuits includes forming an array of transistors using a semiconductor-on-insulator substrate. Electrically isolated arrays of vertically extending, electrically conductive wires are formed from a doped, electrically conductive layer within the substrate, each of the arrays of wires being electrically connected to a transistor in the array of transistors.

Abstract: Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

Abstract: A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.