Abstract: Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.

Abstract: The present disclosure discloses a semiconductor structure and a forming method thereof. The forming method includes: providing a base, where the base is provided with a plurality of bit line isolation trenches extending along a first direction and an isolation structure located in the bit line isolation trench; performing a patterned etching on the base to form a plurality of word line isolation trenches extending along a second direction, where the plurality of bit line isolation trenches and the plurality of word line isolation trenches form a plurality of semiconductor pillars in the base; forming a bit line metal layer on a surface of the semiconductor pillar under the word line isolation trenches, where the bit line metal layer surrounds a sidewall of the semiconductor pillar.

Abstract: Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, and bit lines, word lines, active pillars, and a memory structure that are located on the base. The bit line extends along a first direction, the word line extends along a second direction, the first direction is one of a direction perpendicular to a surface of the base or a direction parallel to the surface of the base, and the second direction is the other of the direction perpendicular to the surface of the base or the direction parallel to the surface of the base. The active pillars are parallel to the base and arranged at intervals, the word line surrounds a channel region of the active pillar, the memory structure surrounds a support region of the active pillar.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars on the substrate, where each of the active pillars includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same, and relate to the field of semiconductor technology. The method includes: providing a substrate provided with word line trenches and bit line trenches, where the word line trenches and the bit line trenches separate the substrate into active pillars arranged at intervals, and along a first direction, a dielectric layer is provided between adjacent active pillars; forming initial protective layers on side walls of the word line trenches; forming word line isolation structures in the region surrounded by the initial protective layers, the word line isolation structures having gaps therein; forming sealing members configured to seal up at least tops of the gaps; forming first filling regions; and forming word lines extending along the first direction in the first filling regions. Parasitic capacitance is prevented in the semiconductor structure, and performance of the semiconductor structure is improved.

Abstract: The present disclosure relates to a memory and a memory forming method. The memory forming method includes: providing an initial substrate; etching the initial substrate to form a plurality of capacitor holes and a plurality of recesses that are connected to the capacitor holes in a one-to-one corresponding manner and located below the capacitor holes; forming an isolation layer that connects adjacent ones of the recesses and fills up the recesses, and using the initial substrate remaining below the isolation layer as a substrate; and forming a capacitor in the capacitor hole.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes: forming a plurality of first trenches extending in a first direction on the substrate; forming a plurality of second trenches extending in a second direction on the substrate; forming a first isolation layer in at least one of the first trenches and at least one of the second trenches, first gaps are respectively provided between the first isolation layer and sidewalls on both sides of the first trench; forming two bit lines which are parallel to each other and extend in the first direction by depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of the first trench; and forming word lines extending in the second direction in the first trench and the second trench, and above the conductive layers in the first trench.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, bit lines, and word lines. The capacitor structure is arranged on the substrate, the transistor structure is arranged on a side of the capacitor structure, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word lines, and other one of the source and the drain of the transistor structure is electrically connected to the bit lines. A word line isolation structure is arranged between adjacent two of the word lines, and a bit line isolation structure is arranged between adjacent two of the bit lines. A width of the word line isolation structure is not equal to a width of the bit line isolation structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; pre-processing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.

Abstract: Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate, the substrate being provided with a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, and a depth of each of the plurality of first trenches being less than a depth of each of the plurality of second trenches; forming a first isolation structure to cover the substrate and fill the plurality of first trenches and the plurality of second trenches; forming a plurality of third trenches positioned in the substrate at bottoms of the plurality of first trenches and extending along the first direction; forming a second isolation structure to fill the plurality of first trenches and the plurality of third trenches; forming gate structures surrounding the substrate between the plurality of first trenches along the second direction.

Abstract: A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Abstract: A semiconductor structure includes a substrate, a gate structure, a cover layer and a first sacrificial structure. The substrate includes discrete semiconductor channels arranged at a top of the substrate. The gate structure is disposed in a middle region of a semiconductor channel, and includes a ring structure and a bridge structure. The ring structure encircles the semiconductor channel, and the bridge structure penetrates through the semiconductor channel and extends to an inner wall of the ring structure along a penetrating direction. The cover layer is located between adjacent semiconductor channels, and includes a first communication hole. The first sacrificial structure is located on the cover layer, and includes a second communication hole. An inner sidewall of the second communication hole has an irregular shape.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.

Abstract: Embodiments relate to a method for fabricating a semiconductor structure. The method includes: providing a substrate, where pillars arranged in an array are formed on a surface of the substrate, and bit lines extending along a first direction are formed at bottoms of the pillars; forming, between adjacent two of the pillars, a first groove extending along a second direction; forming an isolation layer on the substrate, where the isolation layer is filled in the first groove and is filled between adjacent two of the bit lines; etching the isolation layer to expose a surface of the pillar, where a first sub isolation layer positioned in the first groove is lower than a second sub isolation layer; forming a word line surrounding a side wall of the pillar, where a surface of the word line is not higher than a surface of the second sub isolation layer; and forming a dielectric layer on the word line.