Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first stacked structure is disposed on the substrate, and includes a memory cell array; a plurality of word lines (WLs), arranged at intervals and extending along a first direction; a plurality of bit lines (BLs), arranged at intervals and extending along a second direction, one end of each of the plurality of BLs away from the memory cell array forms a step in the first direction, each BL is provided with a groove on a surface of the step, and the second direction and the first direction cross each other; and a plurality of BL plugs, arranged at intervals and extending along the first direction, one end of each BL plug is correspondingly disposed in the groove of one of the BLs.

Abstract: The present disclosure provides a transistor and a manufacturing method thereof, and a memory, relates to the technical field of semiconductors. The transistor includes: a channel, wherein an accommodation space is formed therein; a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space; a dielectric layer, located between the gate and a channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and the source, the drain, and the channel are each made of a semiconductor material.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.

Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

Abstract: Embodiments relate to a semiconductor structure and a formation method. The formation method includes: forming a first active layer on a side of the substrate; forming a first word line in each of the plurality of active areas; forming a first bit line and a conductive contact plug on a top of the first active layer; forming a gate dielectric layer on a side of the first active layer, a side of the first bit line, and a side of the conductive contact plug facing away from the substrate, respectively; forming a second active layer on a side of the gate dielectric layer facing away from the substrate; and forming a second bit line and a second word line on a side of the second active layer facing away from the substrate, where the second bit line and the second word line touch and connect the second active layer, respectively.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, where the substrate includes first grooves arranged at intervals therein along a first direction and a filling layer in the first groove; patterning the substrate, to form second grooves, where the second groove is located on a top surface of the first groove, forming a protective layer on a surface of the substrate, where the protective layer is different from the filling layer; forming a bit line structure at a bottom of the second groove; forming a first isolation layer, where the first isolation layer is located in the second groove and on a top surface of the bit line structure; partially removing the filling layer, where the retained filling layer is flush with an upper surface of the first isolation layer.

Abstract: Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Abstract: A method for forming a three-dimensional memory provided by embodiments includes: forming a substrate and a stacked layer, where the stacked layer includes first semiconductor layers and second semiconductor layers alternately stacked, a thickness of the second semiconductor layers is D1, the first semiconductor layers include a plurality of channel regions as well as a first region and a second region arranged on opposite two sides of each of the plurality of channel regions along a first direction, and the first direction is a direction parallel to the top surface of the substrate; forming a plurality of first openings respectively exposing the plurality of channel regions, a gap between adjacent two of the plurality of first openings along a second direction has a width D2, D1>D2; and depositing a conductive layer along the plurality of first openings.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, and bit lines, word lines, active pillars, and a memory structure that are located on the base. The bit line extends along a first direction, the word line extends along a second direction, the first direction is one of a direction perpendicular to a surface of the base or a direction parallel to the surface of the base, and the second direction is the other of the direction perpendicular to the surface of the base or the direction parallel to the surface of the base. The active pillars are parallel to the base and arranged at intervals, the word line surrounds a channel region of the active pillar, the memory structure surrounds a support region of the active pillar.

Abstract: A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.

Abstract: The present disclosure provides a method of manufacturing a capacitor, a capacitor, and a memory, and relates to the technical field of semiconductors. The method of manufacturing a capacitor includes: providing a substrate; forming a first electrode on the substrate, the first electrode extending in a first direction parallel to the substrate, a size of the first electrode in the first direction being greater than a size of the first electrode in a second direction and a size of the first electrode in a third direction, and every two of the first direction, the second direction, and the third direction being perpendicular to each other; forming a dielectric layer wrapping the first electrode; and forming a second electrode wrapping the dielectric layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with en edge of a respective one of the channel areas in the second direction.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; and forming a plurality of columns of stacked structures arranged at intervals in a first direction on the substrate, each stacked structures including a plurality of first sacrificial layers and a plurality of active layers that are stacked alternately. Part of each of the first sacrificial layers is removed to form a first trench and a second trench, and part of each of the active layers is exposed from the first trench and the second trench. Next, the exposed active layers are doped by ion doping to form first doped areas and second doped areas.

Abstract: A three-dimensional memory and a method for forming the same are provided. The three-dimensional memory includes a substrate, a plurality of word lines and a plurality of lead lines. The word lines are located on the substrate. Each of the word lines extends in a first direction, and includes a first end and a second end opposite to the first end along the first direction. The lead lines are located on the substrate and are connected to the word lines in one-to-one correspondence. There are at least two adjacent word lines, in which the lead line connected to one of the at least two adjacent word lines is located at the first end, and the lead line connected to the other one of the at least two adjacent word lines is located at the second end.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base including bit lines arranged at intervals and extending along a first direction, and a semiconductor channel located on partial top surfaces of the bit lines, where along a direction from the bit line to the semiconductor channel, the semiconductor channel includes a first region, a second region, and a third region that are arranged sequentially; a dielectric layer located between adjacent two of the bit lines and on a sidewall of the semiconductor channel; a gate structure at least surrounding the dielectric layer in the second region and extending along a second direction, where the first direction is different from the second direction; an electrical connection layer covering a top surface of the third region and extending to a partial sidewall of the semiconductor channel.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.

Abstract: A semiconductor structure includes a substrate and multiple word lines located on a top surface of the substrate. Each of the word lines extends in a direction parallel to the top surface of the substrate. The multiple word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate. Any two adjacent word lines are at least partially staggered with respect to one another in the direction perpendicular to the top surface of the substrate.

Abstract: A semiconductor structure and a fabricating method are provided. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and a spacer. The active pillars are positioned on the substrate and are arranged in an array, and the active pillars extend along a direction perpendicular to the substrate. The gate structures are arranged at intervals along a first direction, and the gate structures are arranged surrounding a part of the active pillars. The metal silicide layer is positioned on a top surface of the active pillar, and a projection of the metal silicide layer on the substrate is overlapped with a projection of the top surface of the active pillar on the substrate. The spacer is positioned between adjacent gate structures and adjacent active pillars, and a height of the spacer is higher than a height of a top surface of the metal silicide layer.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.