Patents by Inventor Debendra Das Sharma

Debendra Das Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POOLED MEMORY ADDRESS TRANSLATION
    Publication number: 20210109879
    Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
    Publication number: 20210097015
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUREMENT
    Publication number: 20210089418
    Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • ADJUSTABLE RETIMER BUFFER
    Publication number: 20210089421
    Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING
    Publication number: 20210081288
    Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • REDUCED PIN COUNT INTERFACE
    Publication number: 20210056067
    Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 25, 2021
    Applicant: Intel Corporation
    Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
  • CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTERCONNECTS
    Publication number: 20210050941
    Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Per E. Fornberg, Tal Israeli, Zuoguo Wu
  • PARTIAL LINK WIDTH STATES FOR MULTILANE LINKS
    Publication number: 20210042248
    Abstract: Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Sharing memory and I/O services between nodes
    Patent number: 10915468
    Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
  • RECALIBRATION OF PHY CIRCUITRY FOR THE PCI EXPRESS (PIPE) INTERFACE BASED ON USING A MESSAGE BUS INTERFACE
    Publication number: 20210034565
    Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
    Type: Application
    Filed: July 10, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Fulvio Spagna, Bruce A. Tennant, Noam Dolev Geldbard
  • Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Packets for Computer Buses
    Publication number: 20210013999
    Abstract: Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Swadesh Choudhary, Debendra Das Sharma, Mahesh Wagh
  • FORWARD ERROR CORRECTION MECHANISM FOR PERIPHERAL COMPONENT INTERCONNECT-EXPRESS (PCI-E)
    Publication number: 20210006349
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
    Publication number: 20200409896
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Pooled memory address translation
    Patent number: 10877916
    Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Bypassing equalization at lower data rates
    Patent number: 10880137
    Abstract: A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 29, 2020
    Assignee: INTEL CORPORATION
    Inventor: Debendra Das Sharma
  • HIGH PERFORMANCE INTERCONNECT
    Publication number: 20200394151
    Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
  • Adjustable retimer buffer
    Patent number: 10860449
    Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • Inter-die passive interconnects approaching monolithic performance
    Patent number: 10854548
    Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Adel A. Elsherbini, Gerald Pasdast
  • Cross-talk generation in a multi-lane link during lane testing
    Patent number: 10853212
    Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • FORWARD ERROR CORRECTION MECHANISM FOR DATA TRANSMISSION ACROSS MULTI-LANE LINKS
    Publication number: 20200374037
    Abstract: Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma