Abstract: A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Abstract: A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Abstract: A VCSEL structure is provided. The VCSEL structure comprises a substrate. The structure may also include one or more conducting layers positioned on the substrate. There may be void spaces positioned between portions of the conducting layers to electrically isolate the portions. A method for fabricating the VCSEL structure is also provided.

Abstract: A process for preparing a semiconductor light-emitting device for mounting is disclosed. The light-emitting device has a mounting face for mounting to a sub-mount. The process involves treating at least one surface of the light-emitting device other than the mounting face to lower a surface energy of the at least one surface, such that when mounting the light-emitting device, an underfill material applied between the mounting face and the sub-mount is inhibited from contaminating the at least one surface.

Abstract: A VCSEL structure is provided. The VCSEL structure comprises a substrate. The structure may also include one or more conducting layers positioned on the substrate. There may be void spaces positioned between portions of the conducting layers to electrically isolate the portions. A method for fabricating the VCSEL structure is also provided.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: A VCSEL structure is provided. The VCSEL structure comprises a substrate consisting of a III-V material. The structure may also include one or more conducting layers positioned on said substrate. There may be void spaces positioned between portions of the conducting layers to electrically isolate the portions. A method for fabricating the VCSEL structure is also provided.

Abstract: A vertical cavity laser apparatus is provided. In one embodiment, the apparatus includes an electrically responsive substrate; a support block positioned on the electrically responsive substrate; a bridge arm structure coupled to the support block, the structure having a base; a laser active area on the bridge arm structure, a tuning pad on the bridge arm structure, a laser bond pad on the bridge arm structure with traces connecting the laser bond pad to the laser active area and base. The traces are positioned and shaped to be symmetric to avoid problems due to the asymmetry of the injection current. Additionally, in this embodiment, the laser bond pad is kept at a height of the base in order to minimize device capacitance and the traces are also kept at the height of the base. Methods are also provided whereby impedance matching and high speed performance can be accomplished irregardless of the mechanical configuration of the bridge arm structure.

Abstract: A VCSEL structure is provided. The VCSEL structure comprises a substrate consisting of a III-V material. The structure may also include one or more conducting layers positioned on said substrate. There may be void spaces positioned between portions of the conducting layers to electrically isolate the portions. A method for fabricating the VCSEL structure is also provided.

Abstract: A vertical cavity laser apparatus is provided. In one embodiment, the apparatus includes an electrically responsive substrate; a support block positioned on the electrically responsive substrate; a bridge arm structure coupled to the support block, the structure having a base; a laser active area on the bridge arm structure, a tuning pad on the bridge arm structure, a laser bond pad on the bridge arm structure with traces connecting the laser bond pad to the laser active area and base. The traces are positioned and shaped to be symmetric to avoid problems due to the asymmetry of the injection current. Additionally, in this embodiment, the laser bond pad is kept at a height of the base in order to minimize device capacitance and the traces are also kept at the height of the base. Methods are also provided whereby impedance matching and high speed performance can be accomplished irregardless of the mechanical configuration of the bridge arm structure.

Abstract: A light emitting device having a stack of layers bonded to an undoped substrate with a doped layer between the stack of layers and the undoped substrate. The stack of layers include a layer of first conductivity type over the doped layer, an overlying light emitting layer and a layer of second conductivity type. In one embodiment, the doped substrate is grown on a sacrificial substrate along with the remaining stack of layers prior to bonding to the undoped substrate. Electrical contacts are coupled to device on a side opposite the undoped substrate. In one embodiment, the layers of first conductivity, the light emitting layer, and the layer of second conductivity are removed to expose the doped layer and a first electrical contact is coupled to the layer of first conductivity through the doped substrate, while a second electrical contact is coupled to the layer of second conductivity.

Abstract: A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of the semiconductor light emitting device is plated on either a metal layer formed on the mount or a metal layer formed on one of the contacts. The plated metal layer may replace other known interconnecting techniques such as stud bumps. The semiconductor light emitting device is physically connected to the mount by causing interdiffusion between the contact surfaces of the metal layers. In some embodiments, a layer of solder is formed over the plated metal layer, and then the semiconductor light emitting device is physically connected to the mount by heating the solder.

Abstract: A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Abstract: A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of the semiconductor light emitting device is plated on either a metal layer formed on the mount or a metal layer formed on one of the contacts. The plated metal layer may replace other known interconnecting techniques such as stud bumps. The semiconductor light emitting device is physically connected to the mount by causing interdiffusion between the contact surfaces of the metal layers. In some embodiments, a layer of solder is formed over the plated metal layer, and then the semiconductor light emitting device is physically connected to the mount by heating the solder.

Abstract: A process for preparing a semiconductor light-emitting device for mounting is disclosed. The light-emitting device has a mounting face for mounting to a sub-mount. The process involves treating at least one surface of the light-emitting device other than the mounting face to lower a surface energy of the at least one surface, such that when mounting the light-emitting device, an underfill material applied between the mounting face and the sub-mount is inhibited from contaminating the at least one surface.

Abstract: An out-of-plane micro-structure which can be used for on-chip integration of high-Q inductors and transformers places the magnetic field direction parallel to the substrate plane without requiring high aspect ratio processing. The photolithographically patterned coil structure includes an elastic member having an intrinsic stress profile. The intrinsic stress profile biases a free portion away from the substrate forming a loop winding. An anchor portion remains fixed to the substrate. The free portion end becomes a second anchor portion which may be connected to the substrate via soldering or plating. A series of individual coil structures can be joined via their anchor portions to form inductors and transformers.