Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors and forming a plurality of logic gates; a first intermediate metal layer overlaying the at least one metal layer; a second intermediate metal layer overlaying the first intermediate metal layer; where the first intermediate metal layer has a first current carrying capacity, where the second intermediate metal layer has a second current carrying capacity, and where the first current carrying capacity is significantly greater than the second current carrying capacity; a plurality of second transistors overlaying the second intermediate metal layer; and a top metal layer overlaying the second transistors; and a memory cell, where at least one of the second transistors includes a polysilicon transistor channel, where the second transistors are precisely aligned to the first transistors.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors overlaying the at least one metal layer; a plurality of third transistors overlaying the second transistors; a top metal layer overlaying the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

Abstract: A 3D semiconductor device, the device including: a substrate including a single crystal layer; a plurality of first transistors in and on the single crystal layer; at least one metal layer, where the at least one metal layer overlays the plurality of first transistors and the at least one metal layer includes connections between the first transistors, and where a portion of the connections between the first transistors form memory peripheral circuits; a stack of at least sixteen layers, where the stack of sixteen layers includes odd numbered layers and even numbered layers of a different composition and overlays the at least one metal layer, a multilevel memory structure, where the multilevel memory structure includes the stack of at least sixteen layers, where the stack of at least sixteen layers includes at least eight layers of memory cells controlled by the memory peripheral circuits.

Abstract: A 3D semiconductor, the device including: a first level including a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors overlaying the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly overlaying the NAND logic structure; a memory cell; and a second metal layer overlaying the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 40 nm misalignment, where the second transistors include a p type source and a p type drain.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

Abstract: A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.

Abstract: A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the dev

Abstract: A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

Abstract: A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.