Abstract: Systems and methods of converting text into learning videos and assessments in different languages are described. A system receives content in a first language, then conducts a sentiment analysis in that first language. The system then translates the content into a second language, and generates (via a text-to-speech algorithm) second language speech based on the translated content. The system transliterates the second language speech into the first language, producing one or more visemes, and determines facial expressions of an animated avatar speaking the second language speech using the sentiment analysis results and the one or more visemes. The system then generates an animated presentation with the animated avatar having the facial expressions while speaking the second language speech.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training machine learning systems. One of the methods includes receiving a plurality of training examples; and training a machine learning system on each of the plurality of training examples to determine trained values for weights of a machine learning model, wherein training the machine learning system comprises: assigning an initial value for a regularization penalty for a particular weight for a particular feature; and adjusting the initial value for the regularization penalty for the particular weight for the particular feature during the training of the machine learning system.

Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: The present disclosure relates to a system and method of performing quantization of a neural network having multiple layers. The method comprises receiving a floating-point dataset as input dataset and determining a first shift constant for first layer of the neural network based on the input dataset. The method also comprises performing quantization for the first layer using the determined shift constant of the first layer. The method further comprises determining a next shift constant for next layer of the neural network based on output of a layer previous to the next layer, and performing quantization for the next layer using the determined next shift constant. The method further comprises iterating the steps of determining shift constant and performing quantization for all layers of the neural network to generate fixed point dataset as output.

Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.

Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.

Abstract: Methods, systems, and computer readable storage media for using image processing to develop a library of facial expressions. The system can receive digital video of at least one speaker, then execute image processing on the video to identify landmarks within facial features of the speaker. The system can also identify vectors based on the landmarks, then assign each vector to an expression, resulting in a plurality of speaker expressions. The system then scores the expressions based on similarity to one another, and creates subsets based on the similarity scores.

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

Abstract: A dampened hinge construction for braking pivoting movement of one structure relative to another. The dampened hinge construction can be utilized in a folding table assembly in an aircraft passenger suite including a base panel and at least one folding panel pivotally attached to the base panel by multiple dampened hinges. Each dampened hinge includes a first assembly attachable to a first structure and a second assembly attachable to a second structure such that the first structure is pivotable relative to the second structure between a first condition and a second condition, such as a folded condition and a planar condition, and at least one damper that brakes pivoting movement of the first structure relative to the second structure as the first condition or second condition is approached.

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

Abstract: A system is disclosed. The system includes a passenger seat. The passenger seat includes a seatback comprising one or more guide tracks and a headrest configured to couple to the seatback. The headrest includes a head portion and a lumbar portion. The lumbar portion is configured to separate from the head portion and translate to a lumbar portion of the seatback. The lumbar portion includes one or more brackets configured to slide along the one or more guide tracks. The passenger seat further includes a translation assembly mechanically coupled to the seatback and the lumbar portion. The translation assembly includes a cable coupled to the one or more brackets, wherein a movement of the cable corresponds to a translation of the lumbar portion. The translation assembly further includes a cable route. The translation assembly further includes one or more pulleys configured to guide the cable through the cable route.

Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: This document describes techniques (400, 500, 600) and apparatuses (100, 700) for implementing sensor-based near-field communication (NFC) authentication. These techniques (400, 500, 600) and apparatuses (100, 700) enable a computing device (102) to detect, in a low-power state, environmental variances indicating proximity with an NFC-enabled device (104) with which to authenticate. In some embodiments, various components of a computing device (102) in a sleep state are activated to process environmental variance(s), perform authentication operations, and/or an indicate initiation of authentication operations to a user.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.