Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

Abstract: Systems and techniques are disclosed for generating entries for a searchable index based on rules generated by one or more machine-learned models. The index entries can include one or more tokens correlated with an outcome and an outcome probability. A subset of tokens can be identified based on the characteristics of an event. The index may be searched for outcomes and their respective probabilities that correspond to tokens that are similar to or match the subset of tokens based on the event.

Abstract: A system for implicit authentication for a mobile device associated with a user, wherein the implicit authentication is behavioural, biometric and task-based and includes at least one authentication task selected so as to leverage the user's muscle memory. The mobile device comprises a touchscreen; a transaction authentication information unit; one or more sensors coupled to the transaction authentication information unit; and an anomaly detector coupled to the transaction authentication information unit. The sensors comprise one or more touchscreen sensors coupled to the touchscreen, an accelerometer, and a gyroscope, and are used to obtain and transmit one or more sets of data to the transaction authentication information unit. The sets of data are associated with one or more performances of the authentication task by the user. The anomaly detector generates an authentication model using the one or more data sets transmitted to the transaction authentication information unit.

Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A system for implicit authentication for a mobile device associated with a user, wherein the implicit authentication is behavioral, biometric and task-based and includes at least one authentication task selected so as to leverage the user's muscle memory. The mobile device comprises a touchscreen; a transaction authentication information unit; one or more sensors coupled to the transaction authentication information unit; and an anomaly detector coupled to the transaction authentication information unit. The sensors comprise one or more touchscreen sensors coupled to the touchscreen, an accelerometer, and a gyroscope, and are used to obtain and transmit one or more sets of data to the transaction authentication information unit. The sets of data are associated with one or more performances of the authentication task by the user. The anomaly detector generates an authentication model using the one or more data sets transmitted to the transaction authentication information unit.

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A method for operating an automated food making apparatus having a motor, actuator arm, and an apparatus. The apparatus may be a paddle with flexible fins. The method rotates the paddle with a pin-shaft mechanism to dispense an ingredient placed in a canister, controls the motor automatically based on weight sensor readings, and locates a position of the actuator arm with position sensors. The same motor dispenses ingredients from a plurality of canisters. The method may have a plurality of paddle rotation and weight measurement steps until a target weight is reached. The plurality of paddle rotation steps may be unidirectional or bidirectional paddle rotation. The paddle may be rotated according to one or more paddle rotation algorithms, an error recovery algorithm, or different algorithms based on the amounts of ingredients remaining in the canister. The paddle may be rocked until the target weight is achieved.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training a factorization model to learning features of model inputs of a trained model such that the factorization model is predictive of outcome for which the machine learned model is trained.

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: The present disclosure provides methods and systems for using variable length representations of machine learning statistics. A method may include storing an n-bit representation of a first statistic at a first n-bit storage cell. A first update to the first statistic may be received, and it may be determined that the first update causes a first loss of precision of the first statistic as stored in the first n-bit storage cell. Accordingly, an m-bit representation of the first statistic may be stored at a first m-bit storage cell based on the determination. The first m-bit storage cell may be associated with the first n-bit storage cell. As a result, upon receiving an instruction to use the first statistic in a calculation, a combination of the n-bit representation and the m-bit representation may be used to perform the calculation.

Abstract: Authenticating users comprises a computing device that receives a manual authentication input of a user and initiates a first user session between the user and the user computing device. The device communicates a request for a first user authorization data from an authentication technology associated with the one or more computing devices and receives the first user authentication data. The user or the device terminates the first user session and subsequently receives an input of the user to initiate a second user session. The device communicates a request for second user authentication data from the authentication technology and compares the first user authentication data and the second user authentication data. The device identifies a match of one or more features of the first user authentication data and one or more features of the second user authentication data and authorizes the user to conduct the second user session.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: This document describes techniques (400, 500, 600) and apparatuses (100, 700) for implementing low-power near-field communication (NFC) authentication. These techniques (400, 500, 600) and apparatuses (100, 700) enable a computing device (102) to detect, in a low-power state, an NFC-enabled device (104) with which to authenticate via NFC. In some embodiments, various components of a computing device (102) in a sleep state are activated to perform authentication and/or an indication is provided to a user indicating an initiation of the authentication.