Patents by Inventor Deepak Chandra

Deepak Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10187799
    Abstract: A system for implicit authentication for a mobile device associated with a user, wherein the implicit authentication is behavioral, biometric and task-based and includes at least one authentication task selected so as to leverage the user's muscle memory. The mobile device comprises a touchscreen; a transaction authentication information unit; one or more sensors coupled to the transaction authentication information unit; and an anomaly detector coupled to the transaction authentication information unit. The sensors comprise one or more touchscreen sensors coupled to the touchscreen, an accelerometer, and a gyroscope, and are used to obtain and transmit one or more sets of data to the transaction authentication information unit. The sets of data are associated with one or more performances of the authentication task by the user. The anomaly detector generates an authentication model using the one or more data sets transmitted to the transaction authentication information unit.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 22, 2019
    Assignee: Zighra Inc.
    Inventors: Deepak Chandra Dutt, Anil Buntwal Somayaji, Michael John Kendal Bingham
  • Publication number: 20180374855
    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
    Type: Application
    Filed: February 13, 2018
    Publication date: December 27, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Chandra Mouli, Sanh D. Tang
  • Publication number: 20180374531
    Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Deepak Chandra Pandey, Chandra Mouli, Haitao Liu
  • Publication number: 20180330782
    Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Applicant: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra SEKAR, Wayne Frederick ELLIS, Brent Steven HAUKNESS, Gary Bela BRONNER, Thomas VOGELSANG
  • Publication number: 20180310773
    Abstract: A method for operating an automated food making apparatus having a motor, actuator arm, and an apparatus. The apparatus may be a paddle with flexible fins. The method rotates the paddle with a pin-shaft mechanism to dispense an ingredient placed in a canister, controls the motor automatically based on weight sensor readings, and locates a position of the actuator arm with position sensors. The same motor dispenses ingredients from a plurality of canisters. The method may have a plurality of paddle rotation and weight measurement steps until a target weight is reached. The plurality of paddle rotation steps may be unidirectional or bidirectional paddle rotation. The paddle may be rotated according to one or more paddle rotation algorithms, an error recovery algorithm, or different algorithms based on the amounts of ingredients remaining in the canister. The paddle may be rocked until the target weight is achieved.
    Type: Application
    Filed: April 4, 2018
    Publication date: November 1, 2018
    Inventors: Deepak Chandra Sekar, Kathirgugan Kathirasen, Brian Richardson, Sanath Bhat
  • Patent number: 10102482
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training a factorization model to learning features of model inputs of a trained model such that the factorization model is predictive of outcome for which the machine learned model is trained.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: October 16, 2018
    Assignee: Google LLC
    Inventors: Heng-Tze Cheng, Jeremiah Harmsen, Alexandre Tachard Passos, David Edgar Lluncor, Shahar Jamshy, Tal Shaked, Tushar Deepak Chandra
  • Patent number: 10096551
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Publication number: 20180286480
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 4, 2018
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 10062035
    Abstract: The present disclosure provides methods and systems for using variable length representations of machine learning statistics. A method may include storing an n-bit representation of a first statistic at a first n-bit storage cell. A first update to the first statistic may be received, and it may be determined that the first update causes a first loss of precision of the first statistic as stored in the first n-bit storage cell. Accordingly, an m-bit representation of the first statistic may be stored at a first m-bit storage cell based on the determination. The first m-bit storage cell may be associated with the first n-bit storage cell. As a result, upon receiving an instruction to use the first statistic in a calculation, a combination of the n-bit representation and the m-bit representation may be used to perform the calculation.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 28, 2018
    Assignee: Google LLC
    Inventors: Tal Shaked, Tushar Deepak Chandra, Yoram Singer, Tze Way Eugene Ie, Joshua Redstone
  • Publication number: 20180225439
    Abstract: Authenticating users comprises a computing device that receives a manual authentication input of a user and initiates a first user session between the user and the user computing device. The device communicates a request for a first user authorization data from an authentication technology associated with the one or more computing devices and receives the first user authentication data. The user or the device terminates the first user session and subsequently receives an input of the user to initiate a second user session. The device communicates a request for second user authentication data from the authentication technology and compares the first user authentication data and the second user authentication data. The device identifies a match of one or more features of the first user authentication data and one or more features of the second user authentication data and authorizes the user to conduct the second user session.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventor: Deepak Chandra
  • Patent number: 10037801
    Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 31, 2018
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
  • Patent number: 9983651
    Abstract: This document describes techniques (400, 500, 600) and apparatuses (100, 700) for implementing low-power near-field communication (NFC) authentication. These techniques (400, 500, 600) and apparatuses (100, 700) enable a computing device (102) to detect, in a low-power state, an NFC-enabled device (104) with which to authenticate via NFC. In some embodiments, various components of a computing device (102) in a sleep state are activated to perform authentication and/or an indication is provided to a user indicating an initiation of the authentication.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 29, 2018
    Assignee: GOOGLE TECHNOLOGY HOLDINGS LLC
    Inventors: Jagadish Kumar Agrawal, Deepak Chandra, John J. Gorsica, Jagatkumar V. Shah
  • Publication number: 20180137914
    Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 17, 2018
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis
  • Publication number: 20180130807
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 10, 2018
    Inventor: Deepak Chandra Pandey
  • Patent number: 9965609
    Abstract: Authenticating users comprises a computing device that receives a manual authentication input of a user and initiates a first user session between the user and the user computing device. The device communicates a request for a first user authorization data from an authentication technology associated with the one or more computing devices and receives the first user authentication data. The user or the device terminates the first user session and subsequently receives an input of the user to initiate a second user session. The device communicates a request for second user authentication data from the authentication technology and compares the first user authentication data and the second user authentication data. The device identifies a match of one or more features of the first user authentication data and one or more features of the second user authentication data and authorizes the user to conduct the second user session.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 8, 2018
    Assignee: GOOGLE LLC
    Inventor: Deepak Chandra
  • Patent number: 9941005
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 9935949
    Abstract: Embodiments are provided for mutually authenticating a pair of electronic devices. According to certain aspects, the electronic devices may connect to each other via an out-of-band communication channel. The electronic devices may each output audio signals and detect audio signals output by the other electronic devices. Based on timestamps associated with audio output and detection events, each of the electronic devices may calculate relevant time and distance parameters, and transmit the calculated parameters to the other electronic device via the out-of-band communication channel. The electronic devices may compare the calculated parameters to determine mutual authentication.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 3, 2018
    Assignee: GOOGLE LLC
    Inventors: Michael Daley, Peiter Zatko, Deepak Chandra
  • Publication number: 20180007553
    Abstract: A system for implicit authentication for a mobile device associated with a user, wherein the implicit authentication is behavioural, biometric and task-based and includes at least one authentication task selected so as to leverage the user's muscle memory. The mobile device comprises a touchscreen; a transaction authentication information unit; one or more sensors coupled to the transaction authentication information unit; and an anomaly detector coupled to the transaction authentication information unit. The sensors comprise one or more touchscreen sensors coupled to the touchscreen, an accelerometer, and a gyroscope, and are used to obtain and transmit one or more sets of data to the transaction authentication information unit. The sets of data are associated with one or more performances of the authentication task by the user. The anomaly detector generates an authentication model using the one or more data sets transmitted to the transaction authentication information unit.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Deepak Chandra Dutt, Anil Buntwal Somayaji, Michael John Kendal Bingham
  • Publication number: 20170358532
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Application
    Filed: August 3, 2017
    Publication date: December 14, 2017
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Patent number: 9842840
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Deepak Chandra Pandey