Patents by Inventor DeokKyung Yang

DeokKyung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842991
    Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: December 12, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, OhHan Kim, HeeSoo Lee, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Publication number: 20230268289
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Deokkyung Yang, HeeSoo Lee
  • Patent number: 11676911
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: June 13, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Deokkyung Yang, HeeSoo Lee
  • Patent number: 11670618
    Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 6, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
  • Publication number: 20230154864
    Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee, Wanil Lee, SangDuk Lee
  • Patent number: 11652088
    Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 16, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, SungSoo Kim, HeeSoo Lee
  • Patent number: 11587882
    Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: February 21, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee, Wanil Lee, SangDuk Lee
  • Patent number: 11367690
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 21, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Patent number: 11342294
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 24, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, OhHan Kim, HeeSoo Lee, DaeHyeok Ha, Wanil Lee
  • Publication number: 20220115332
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Deokkyung Yang, HeeSoo Lee
  • Publication number: 20220052025
    Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, SungSoo Kim, HeeSoo Lee
  • Patent number: 11244908
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 8, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Deokkyung Yang, HeeSoo Lee
  • Patent number: 11189598
    Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 30, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, SungSoo Kim, HeeSoo Lee
  • Patent number: 11145603
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 12, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 11024585
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 1, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20210151386
    Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 20, 2021
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee, Wanil Lee, SangDuk Lee
  • Patent number: 10937741
    Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 2, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee, Wanil Lee, SangDuk Lee
  • Publication number: 20200402955
    Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
  • Publication number: 20200373289
    Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, OhHan Kim, HeeSoo Lee, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Patent number: 10797039
    Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 6, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, OhHan Kim, HeeSoo Lee, HunTeak Lee, InSang Yoon, Il Kwon Shim