Patents by Inventor DeokKyung Yang

DeokKyung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083903
    Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: September 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
  • Publication number: 20180269181
    Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 20, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
  • Publication number: 20180261569
    Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, OhHan Kim, HeeSoo Lee, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Patent number: 9997468
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 12, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20180158768
    Abstract: A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 7, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, DeokKyung Yang, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Publication number: 20180158779
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Application
    Filed: November 9, 2017
    Publication date: June 7, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Patent number: 9905491
    Abstract: Semiconductor packages with multiple substrates can incorporate cavities in a portion of an upper substrate to minimize or reduce void formations during a molding process. The cavities can be formed substantially over the integrated circuit devices and not over the internal interconnects to further facilitate the flow of the molding compound. The combination with extension members or recesses on a top or exterior surface of the upper substrate can further cut down on bleeding or spill over of the molding compound between adjacent packages and improve device reliability and yield.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 27, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, SeongHun Mun
  • Patent number: 9748203
    Abstract: A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 29, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, In Sang Yoon, SeongHun Mun, KyungHwan Kim
  • Publication number: 20160300799
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 13, 2016
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 9385066
    Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 5, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
  • Patent number: 9230898
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a component over a side of the substrate; forming an interface module having a module via in any location for connectivity to the substrate; and mounting the entirety of the interface module over a portion of the side of the substrate next to the component.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: January 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HanGil Shin, DeokKyung Yang, Jong-Woo Ha
  • Patent number: 9202715
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 1, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungChul Kim, KyungHoon Lee, Seong Won Park, Ki Youn Jang, JaeHyun Lee, DeokKyung Yang, In Sang Yoon, SungEun Park
  • Patent number: 9184067
    Abstract: Semiconductor packages with multiple substrates can incorporate apertures or slots between devices to minimize or reduce formation of defects during a molding process. The apertures or slots can be formed adjacent a top substrate in alignment with removable regions adjacent a bottom substrate whereby the apertures or slots can facilitate outflow of materials from cavities between the substrates. The apertures or slots may subsequently be removed in conjunction with the removable regions during a singulation process thereby producing the desired semiconductor packages with improved device reliability and yield.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: KyungHwan Kim, DeokKyung Yang, SeongHun Mun, KeoChang Lee
  • Patent number: 9171739
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungDal Roh, DeokKyung Yang, HeeSoo Lee
  • Patent number: 8823160
    Abstract: An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around the external interconnect with the external interconnect exposed from the encapsulation and with the encapsulation and the second side forming a cavity.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: September 2, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, DaeSik Choi, DeokKyung Yang
  • Patent number: 8765525
    Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 1, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
  • Patent number: 8699232
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Patent number: 8633100
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, In Sang Yoon, SangJin Lee
  • Patent number: 8603859
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a top integrated circuit on a first side of the substrate; mounting a bottom integrated circuit on a second side of the substrate; forming a top encapsulation over the top integrated circuit and a bottom encapsulation over the bottom integrated circuit simultaneously; and forming a bottom via through the bottom encapsulation to the substrate.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: December 10, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, DaeSik Choi
  • Patent number: 8592973
    Abstract: A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: November 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: HyungSang Park, DeokKyung Yang, DaeSik Choi