Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.

Abstract: Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.

Abstract: Methods, systems, and devices for dynamic adjustment of bin offsets are described. A memory system may perform a dynamic bin offset adjustment procedure, in which bin offsets configured for read voltage adjustment at the memory system may be adjusted according to performance results of test read operations. For example, the memory system may perform one or more read operations, which may be utilized to adjust each bin offset, for example, by increasing or decreasing the bin offsets over multiple repetitions or over a life cycle of the memory system. The memory system may obtain measurements in response to the one or more read operations to determine whether such adjustments increase read performance and may apply the adjustments to the bin offset values stored at the memory system accordingly.

Abstract: Methods, systems, and devices for reordered page mapping for triple level memory cells are described. A memory system may map logical block addresses (LBAs) to page physical addresses (PPAs) according to a logical-to-physical (L2P) mapping scheme such that a low LBA may be mapped to an upper page of a tri-level cell (TLC). The memory device may receive a write command that includes data associated with a range of LBAs. The range of LBAs may include a lowest LBA and a highest LBA. The memory device may map the range of LBAs to one or more PPAs according to the L2P mapping scheme. The lowest LBA of the range of LBAs may be mapped to a first PPA associated with a UP of a TLC in accordance with the L2P mapping scheme. Then, the memory device may write the data to the TLC according to the L2P mapping scheme.

Abstract: A system includes a memory device having a memory array with memory cells organized into memory blocks, and a processing device coupled to the memory device. The processing device receives a programming command directed to a set of memory cells, the programming command associated with a cell type indicating a number of bits to be stored per memory cell. The processing device determines, based on the cell type, an erase mode corresponding to the cell type, and determines whether a memory block is in an erased state corresponding to the erase mode. Responsive to determining that the memory block is in the erased state corresponding to the erase mode, the processing device performs a programming operation with respect to the set of memory cells. Responsive to determining that the memory block is not in the erased state corresponding to the erase mode, the processing device erases the memory block in the erase mode prior to performing the programming operation.

Abstract: A fluid control assembly and a heat management system are provided. The fluid control assembly comprises a communication channel and heat exchange channels. The heat exchange channels comprise a first channel and a second channel. The communication channel is in communication with a flow channel of a fluid management element. The flow channel of the fluid management element is in communication with the first channel. At least a portion of the first channel is disposed close to at least a portion of the second channel, and working fluid within the portions of the first channel and the second channel which are close to one another can exchange heat.

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

Abstract: A fluid management apparatus and a heat management system are provided. The fluid management apparatus includes a connecting piece and a liquid storage part. The connecting piece and the liquid storage part are arranged separately, and a first mating part of a liquid storage part shell is sealedly connected to a first connecting port portion of the connecting piece. A liquid storage cavity of the liquid storage part is in communication with a flow channel of the connecting piece, and the connecting piece, which is provided with a flow channel, is arranged separately from the liquid storage part.

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Abstract: Methods, systems, and devices for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.

Abstract: Methods, systems, and devices for read disturb detection in a memory system are described. A memory system may perform a read operation on a set of memory cells using a read voltage that is between a first target threshold voltage for the set of memory cells and a second target threshold voltage for the set of memory cells. The memory system may determine, based on a quantity of memory cells with a threshold voltage greater than the read voltage being greater than a threshold quantity, a bit error rate for the set of memory cells. And the memory system may determine whether to perform a refresh operation on the set of memory cells based on the bit error rate for the set of memory cells.

Abstract: Methods, systems, and devices for data transfer during maintenance operations are described. A memory system utilize an auto-suspend feature to parallelize aspects of maintenance operations. For example, the memory system may suspend a programming operation being performed on a first block of memory cells. The memory system may read data from a second block of memory cells while the programming operation is suspended, and may transfer the data from the second block of memory cells (e.g., to a controller) in parallel with resuming the programming operation on the first block of memory cells. The memory system may transfer the data read from the second block of memory cells to a third block of memory cells in parallel with resuming the programming operation on the first block of memory cells.

Abstract: Methods, systems, and devices for critical data management within a memory system are described. A memory system may avoid writing critical data to weak word lines. For example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. The memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. The memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.

Abstract: Methods, systems, and devices for partitioned transferring for write booster are described. Techniques are described for a memory system to transfer data from a buffer associated with a write booster mode to higher-density blocks of the memory system based on a type of the data stored in the buffer. A first type of data may be transferred from the buffer to the higher-density blocks before a second type of data may be transferred from the buffer to the higher-density blocks. Prioritizing the transfer of data from the buffer to the higher-density block based on the type of data may reduce a write amplification associated with the memory system.

Abstract: Methods, systems, and devices for dynamic initialization delay management for a memory system are described. A memory system may perform a power transition operation from a hibernation mode to an active mode in response to a command from a host system. The memory system and host system may refrain from communicating signaling during the power transition operation due to power transition delays. A memory system power transition delay may be dynamically configured based on a host system power transition delay, such that the memory system power transition delay may be initially programmed then updated based on receiving an indication of the host system power transition delay. The host system may transmit the indication of the host system power transition delay during an initial linking operation with the memory system. The memory system may update the memory system power transition delay to be greater than the host system power transition delay.

Abstract: A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.

Abstract: Methods, systems, and devices for voltage monitoring by a memory system are described. An application specific integrated circuit (ASIC) may be configured to provide feedback to one or more controllers of a memory system indicating whether a current sensed from an alternating current (AC) voltage source satisfies a threshold. The ASIC may output a flag in response to the current sensed by the ASIC satisfying the threshold, and the memory system may perform power management operations by adjusting operating parameters in response to the flag. The ASIC may be configured to generate token information that estimates a total current budget for the memory system in accordance with a power consumption at components of the memory system (e.g., AC components, direct current (DC) components, open NAND flash interface (ONFI) components), and the memory system may perform power management operations in response to the total current budget satisfying a threshold.

Abstract: Methods, systems, and devices for address conversion table supporting hardware automation are described. A memory system may implement a hardware logic block to perform the conversion of a logical page address to a physical device address. The hardware logic block may include a set of one or more tables for address conversion, including a page mapping table, a page type change point table, and a virtual block table, which may support performing the conversion of the logical page address to a physical device address using hardware logic. To account for varying parameters of the memory system, the firmware may load one or more parameters for the hardware logic block, for example, during initialization of the memory system. As such, the hardware logic block may support converting logical page addresses to physical device addresses for various different memory systems and memory system configurations.