Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and control circuit coupled with the first and second set of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

Abstract: Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

Abstract: A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.