Patents by Inventor Deping He

Deping He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Erase operations with erase-verify voltages based on where in the erase operations an erase cycle occurs
    Patent number: 8971125
    Abstract: Memory devices and methods of erasing the memory devices are disclosed. One such method includes performing an erase cycle of an erase operation on a plurality of memory cells, where performing the erase cycle of the erase operation includes selecting an erase verify voltage to be applied during the erase cycle from a plurality of erase verify voltages based on where in the erase operation the erase cycle occurs.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Deping He
  • Multiple level program verify in a memory device
    Patent number: 8717823
    Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Taehoon Kim, Deping He, Jeffrey Alan Kessenich
  • ERASE OPERATIONS WITH ERASE-VERIFY VOLTAGES BASED ON WHERE IN THE ERASE OPERATIONS AN ERASE CYCLE OCCURS
    Publication number: 20140003156
    Abstract: Memory devices and methods of erasing the memory devices are disclosed. One such method includes performing an erase cycle of an erase operation on a plurality of memory cells, where performing the erase cycle of the erase operation includes selecting an erase verify voltage to be applied during the erase cycle from a plurality of erase verify voltages based on where in the erase operation the erase cycle occurs.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventor: Deping He
  • MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE
    Publication number: 20120269004
    Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 25, 2012
    Inventors: Taehoon Kim, Deping He, Jeffrey Alan Kessenich
  • Multiple level program verify in a memory device
    Patent number: 8223555
    Abstract: Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Taehoon Kim, Deping He, Jeffrey Alan Kessenich
  • MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE
    Publication number: 20100284219
    Abstract: Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 11, 2010
    Inventors: Taehoon Kim, Deping He, Jeffrey Alan Kessenich