Patents by Inventor Derek C. Tao
Derek C. Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138359Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: August 31, 2020Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20210288043Abstract: A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jacklyn CHANG, Derek C. TAO, Kuo-Yuan HSU
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Patent number: 11031383Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.Type: GrantFiled: August 14, 2018Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jacklyn Chang, Derek C. Tao, Kuo-Yuan Hsu
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Publication number: 20200394355Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10762269Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20200058634Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.Type: ApplicationFiled: August 14, 2018Publication date: February 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jacklyn CHANG, Derek C. TAO, Kuo-Yuan HSU
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Publication number: 20190325104Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10424587Abstract: A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.Type: GrantFiled: October 24, 2017Date of Patent: September 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. Tao, Jacklyn Chang, Kuoyuan (Peter) Hsu, Yukit Tang
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Patent number: 10339248Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: GrantFiled: December 20, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 10176282Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.Type: GrantFiled: March 4, 2015Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shaojie Xu, Yukit Tang, Pao-Po Hou, Derek C. Tao, Annie-Li-Keow Lum
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Patent number: 10031982Abstract: Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.Type: GrantFiled: December 24, 2014Date of Patent: July 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pao-Po Hou, Derek C. Tao, Liang-Yu Chen, Shaojie Xu, Kuoyuan Hsu
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Publication number: 20180113973Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Publication number: 20180061841Abstract: A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.Type: ApplicationFiled: October 24, 2017Publication date: March 1, 2018Inventors: Derek C. TAO, Jacklyn CHANG, Kuoyuan (Peter) HSU, Yukit TANG
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Patent number: 9852249Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: GrantFiled: July 24, 2013Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 9818752Abstract: A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.Type: GrantFiled: May 13, 2016Date of Patent: November 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. Tao, Jacklyn Chang, Kuoyuan (Peter) Hsu, Yukit Tang
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Patent number: 9779801Abstract: A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.Type: GrantFiled: January 16, 2015Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. Tao, Kuoyuan (Peter) Hsu, Annie-Li-Keow Lum
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Patent number: 9576622Abstract: In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.Type: GrantFiled: January 24, 2014Date of Patent: February 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
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Patent number: 9478269Abstract: A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.Type: GrantFiled: November 14, 2014Date of Patent: October 25, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
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Patent number: 9449681Abstract: A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.Type: GrantFiled: June 23, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie-Li-Keow Lum, Derek C. Tao
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Publication number: 20160254267Abstract: A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.Type: ApplicationFiled: May 13, 2016Publication date: September 1, 2016Inventors: Derek C. TAO, Jacklyn CHANG, Kuoyuan (Peter) HSU, Yukit TANG