Abstract: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

Abstract: A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

Abstract: A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.

Abstract: A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.

Abstract: A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

Abstract: A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.

Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.

Abstract: A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.

Abstract: A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.

Abstract: A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.