Patents by Inventor Derek C. Tao
Derek C. Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8643422Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.Type: GrantFiled: July 12, 2012Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Tsung-Ching Huang, Derek C. Tao
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Publication number: 20140032871Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Bing Wang, Derek C. Tao, Yukit Tang, Kai Fan
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Publication number: 20140015582Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Tsung-Ching HUANG, Derek C. TAO
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Patent number: 8619477Abstract: A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.Type: GrantFiled: July 20, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bing Wang, Kuoyuan (Peter) Hsu, Derek C. Tao
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Patent number: 8619478Abstract: A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.Type: GrantFiled: October 5, 2011Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie-Li-Keow Lum, Derek C. Tao, Bing Wang
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Patent number: 8605523Abstract: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.Type: GrantFiled: February 17, 2012Date of Patent: December 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Derek C. Tao, Young Seog Kim, Kuoyuan (Peter) Hsu, Bing Wang, Annie-Li-Keow Lum
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Publication number: 20130311964Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 8587991Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.Type: GrantFiled: March 23, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Young Seog Kim, Kuoyuan (Peter) Hsu, Derek C. Tao, Young Suk Kim
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Publication number: 20130264718Abstract: A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jacklyn CHANG, Evan Yong ZHANG, Derek C. TAO, Kuoyuan (Peter) HSU
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Patent number: 8519444Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.Type: GrantFiled: September 10, 2010Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20130215693Abstract: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. TAO, Young Seog KIM, Kuoyuan (Peter) HSU, Bing WANG, Annie-Li-Keow LUM
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Patent number: 8450778Abstract: A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.Type: GrantFiled: August 24, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jacklyn Chang, Kuoyuan Hsu, Derek C. Tao
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Publication number: 20130088927Abstract: A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie-Li-Keow Lum, Derek C. Tao, Bing Wang
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Publication number: 20130088925Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jacklyn CHANG, Derek C. TAO, Yukit TANG, Kuoyuan (Peter) HSU
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Publication number: 20130088926Abstract: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. TAO, Annie-Li-Keow LUM, Yukit TANG, Kuoyuan (Peter) HSU
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Patent number: 8406078Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.Type: GrantFiled: February 11, 2011Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Young Seog Kim
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Publication number: 20130010560Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.Type: ApplicationFiled: June 27, 2012Publication date: January 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ji LU, Hung-Jen LIAO, Cheng Hung LEE, Derek C. TAO, Annie-Li-Keow LUM, Hong-Chen CHENG
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Patent number: 8305827Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.Type: GrantFiled: July 13, 2010Date of Patent: November 6, 2012Inventors: Derek C. Tao, Kuoyuan (Peter) Hsu, Dong Sik Jeong, Young Suk Kim, Young Seog Kim, Yukit Tang
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Patent number: 8300491Abstract: A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.Type: GrantFiled: August 26, 2010Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Derek C. Tao, Annie-Li-Keow Lum, Chung-Ji Lu
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Publication number: 20120230127Abstract: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Jung-Ping Yang, Chung-Ji Lu, Derek C. Tao, Cheng Hung Lee, Hung-Jen Liao