Patents by Inventor Devendra K. Sadana

Devendra K. Sadana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367863
    Abstract: A battery includes a cathode with a metal halide and an electrically conductive material, wherein the metal halide acts as an active cathode material; a porous silicon anode with a surface having pores with a depth of about 0.5 microns to about 500 microns, and a metal on the surface and in at least some of the pores thereof; and an electrolyte contacting the anode and the cathode, wherein the electrolyte includes a nitrile moiety.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 21, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jangwoo Kim, Young-Hye Na, Robert David Allen, Joel P. de Souza, John Collins, Devendra K. Sadana
  • Publication number: 20220181535
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.
    Type: Application
    Filed: January 9, 2020
    Publication date: June 9, 2022
    Inventors: Steven J. Holmes, Devendra K. Sadana, Brent A. Wacaser, Damon Farmer
  • Patent number: 11355703
    Abstract: According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana
  • Patent number: 11349061
    Abstract: According to an embodiment of the present invention, a method of producing a computing device includes providing a semiconductor substrate, and patterning a mask on the semiconductor substrate, the mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate. The method includes implanting the first portion of the semiconductor substrate with a dopant. The method includes annealing the first portion of the semiconductor substrate to form an annealed doped region, while maintaining the second portion of the semiconductor substrate as an unannealed portion.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 31, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Brent A. Wacaser, Damon Brooks Farmer
  • Patent number: 11335899
    Abstract: A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 17, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, Ali Afzali-Ardakani, Joel P. de Souza, Teodor K. Todorov, Devendra K. Sadana
  • Patent number: 11322787
    Abstract: An energy storage device has all components, e.g. anode, electrolyte, and cathode contained and sealed with a trench in a substrate. Various methods and structures are disclosed for sealing the components. In some embodiments, a sealer or sealing layer seals the components. One embodiment uses a tension clamp to contain the components with additional pressure. Another embodiment uses a cathode structure cup which is held in place in the substrate via sidewall trench features. Different external connections to the device are disclosed. The invention enables full three-dimensional components to be created and contained entirely within the substrate during assembly, curing, galvanic cycling and other manufacturing processes and provides improved sealing of the components during device operation.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, John M. Papalia, Devendra K. Sadana, Matthew Sagianis
  • Patent number: 11316022
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
  • Patent number: 11316154
    Abstract: A three dimensional (3D) In-Silicon energy storage device is provided by a method that includes forming a thick dielectric material layer on a surface of a silicon based substrate. A 3D trench is then formed into the dielectric material layer and the silicon based substrate, and thereafter a dielectric material spacer is formed, in addition to the dielectric remaining on the field of the substrate, as well as along a sidewall of the 3D trench, and on a first portion of a sub-surface of the silicon based substrate that is present at a bottom of the 3D trench. A second portion of the sub-surface of the silicon based substrate that is present in the 3D trench remains physically exposed. Active energy storage device materials can then be formed laterally adjacent to the dielectric material spacer that is within the 3D trench and on the dielectric material layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, John M. Papalia, David L. Rath, Devendra K. Sadana
  • Patent number: 11309585
    Abstract: An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, Ali Afzali-Ardakani, Teodor K. Todorov, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 11302857
    Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20220102626
    Abstract: A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Inventors: Ning Li, Joel P. de Souza, Kevin W. Brew, Devendra K. Sadana
  • Publication number: 20220052316
    Abstract: A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 17, 2022
    Inventors: John Collins, Teodor Krassimirov Todorov, Ali Afzali-Ardakani, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 11244947
    Abstract: A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 8, 2022
    Assignee: HeFeChip Corporation Limited
    Inventors: John Zhang, Devendra K Sadana, Yanzun Li, Huang Liu
  • Patent number: 11245134
    Abstract: A Lithium energy storage device comprising a cathode, electrolyte, anode, and substrate. The materials contained in the anode and electrolyte region are electrochemically altered during initial formation and exposed to current cycles to create a lower impedance composite anode. The resulting composite anode bottom is a bi-layer comprising: i. a lithium metal layer and ii. a silicon-based interphase layer. The bi-layer acts as a barrier to inhibit Lithium ions from entering or leaving a Lithium saturated substrate, once the interphase surface is formed and the substrate is saturated with Lithium ions. This prevents cell failure from large volume changes/stresses during charge/discharge cycles and enables a significant decrease in cell impedance to enable better rechargeable cell performance.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, Ali Afzali-Ardakani, John M. Papalia, Devendra K. Sadana
  • Patent number: 11233288
    Abstract: A method of forming a semiconductor structure includes forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature. The method also includes forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate. The method further includes forming, in at least a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate. The porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 11233161
    Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11220742
    Abstract: A method of fabricating a glassy carbon film is described. The method includes forming a soluble layer on a substrate, forming a lift-off stack that includes a lift-off mask layer and a hard-mask layer, and forming a pattern in the lift-off stack to expose a portion of the soluble layer. The exposed portions of the soluble layer are removed to expose a portion of the substrate. A carbon material is over the exposed portion of the substrate. The soluble layer is dissolved in a solvent, and the lift-off stack is lifted-off.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Deborah A. Neumayer, Stephen Bedell, Devendra K. Sadana, Damon Farmer, Nathan P. Marchack
  • Patent number: 11217717
    Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11216595
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: January 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Patent number: 11211542
    Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li