Patents by Inventor Devendra K. Sadana

Devendra K. Sadana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252573
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10374159
    Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Tze-bin Song
  • Patent number: 10374389
    Abstract: A plasmonic light source includes a substrate and a square nano-cavity formed on the substrate. The nano-cavity includes a quantum well structure. The quantum well structure includes III-V materials. A plasmonic metal is formed as an electrode on the square nano-cavity and is configured to excite surface plasmons with the quantum well structure to generate light. Complementary metal oxide semiconductor (CMOS) devices are formed on the substrate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 6, 2019
    Assignees: International Business Machines Corporation, The George Washington University
    Inventors: Ning Li, Ke Liu, Devendra K. Sadana, Volker J. Sorger
  • Publication number: 20190232083
    Abstract: Probes include a probe body configured to penetrate biological tissue. High-efficiency light sources are positioned within the probe body. Each high-efficiency light source has a sufficiently intense light output to trigger a light-sensitive reaction in neighboring tissues and has a sufficiently low power output such that a combined heat output of multiple light sources does cause a disruptive temperature increase in the neighboring tissues.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Hariklia Deligianni, Ko-Tao Lee, Ning Li, Devendra K. Sadana
  • Publication number: 20190237511
    Abstract: Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
    Type: Application
    Filed: April 6, 2019
    Publication date: August 1, 2019
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20190237597
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Patent number: 10365240
    Abstract: A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Shu-Jen Han, Ning Li, Devendra K. Sadana
  • Patent number: 10366881
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10367060
    Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Devendra K. Sadana
  • Publication number: 20190221592
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 18, 2019
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Patent number: 10354880
    Abstract: Embodiments herein describe techniques for forming sidewalls on vertical structures on a semiconductor substrate. In one embodiment, the semiconductor substrate includes a first layer (e.g., a conductive layer such as an electrode) on which a second layer (e.g., an insulator) is disposed. An undercut etch is performed which selectively etches the sides of the material in the first layer but not the material in the second layer. A conformal deposition process is used to deposit the material of the sidewall into the undercut regions. Further etches can be performed to shape the sidewalls disposed on the sides of the material in the first layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joel P. De Souza, Yun Seog Lee, Devendra K. Sadana
  • Patent number: 10355164
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20190214475
    Abstract: A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Ning Li, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana
  • Publication number: 20190214413
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Publication number: 20190214519
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 11, 2019
    Inventors: TZE-CHIANG CHEN, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Patent number: 10347779
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Publication number: 20190207000
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 4, 2019
    Inventors: STEPHEN W. BEDELL, NICOLAS J. LOUBET, DEVENDRA K. SADANA
  • Publication number: 20190198696
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10330597
    Abstract: Apparatus for enhancing on-chip fluorescence detection. For example, an apparatus comprises a microfluidic channel, an excitation signal enhancing structure formed on a first side of the microfluidic channel and a photodetector structure formed on a second side of the microfluidic channel. For example, the excitation signal enhancing structure enhances an excitation signal and the enhanced excitation signal excites one or more samples in the microfluidic channel to emit signals at a fluorescence wavelength at a higher rate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yann Andre Nicolas Astier, Ning Li, Devendra K. Sadana, Chao Wang
  • Publication number: 20190189434
    Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken