Abstract: A method of forming a semiconductor structure includes forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature. The method also includes forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate. The method further includes forming, in at least a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate. The porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature.

Abstract: A method of fabricating a glassy carbon film is described. The method includes forming a soluble layer on a substrate, forming a lift-off stack that includes a lift-off mask layer and a hard-mask layer, and forming a pattern in the lift-off stack to expose a portion of the soluble layer. The exposed portions of the soluble layer are removed to expose a portion of the substrate. A carbon material is over the exposed portion of the substrate. The soluble layer is dissolved in a solvent, and the lift-off stack is lifted-off.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.

Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.

Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.

Abstract: A diode is made of a p-type layer and an n-type layer connected in series between a bottom and top electrode. The p-type and n-type layers have a thickness below 20 nm. A p-type dopant concentration and an n-type dopant concentration are high enough to keep a total resistance across the diode at less than 250? when the diode is forward biased while still retaining the characteristics of a diode. In some embodiments, the ratio of an ON current to an OFF current is greater than 2.5×104. Alternate embodiments of the diode, arrays of diodes and methods of making diodes are disclosed. Example arrays include memory arrays using diodes and phase change memories (PCMs) connected in series as array elements. The arrays can be stacked in layers and can be made/embodied in the back-end-of-the line (BEOL).

Abstract: A device such as, for example, an energy storage device or a micro-resistor, is disclosed which includes a silicon based electrode in which decreased interfacial resistance/impedance throughout the charge-mobile region of the device is provided. The decreased interfacial resistance/impedance is provided by forming an interfacial additive composite layer composed of a molten lithium containing salt layer and a layer of a Li-salt containing conductive polymeric adhesive material between the silicon based electrode and a solid polymer electrolyte layer. The presence of such an interfacial additive composite layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

Abstract: According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.

Abstract: Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: According to an embodiment of the present invention, a method of producing a computing device includes providing a semiconductor substrate, and patterning a mask on the semiconductor substrate, the mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate. The method includes implanting the first portion of the semiconductor substrate with a dopant. The method includes annealing the first portion of the semiconductor substrate to form an annealed doped region, while maintaining the second portion of the semiconductor substrate as an unannealed portion.

Abstract: Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.

Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.

Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.

Abstract: According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

Abstract: A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.