Abstract: Single wafer processing methods and systems for manufacturing films having low-k properties and low indices of refraction. The methods incorporate a processing station in which both curing and post-cure, in situ gas cooling take place.

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: Methods and apparatus for plasma-assisted joining of one or more parts together are provided. The joining process may include, for example, placing at least first and second joining areas in proximity to one another in a cavity, forming a plasma in the cavity by subjecting a gas to electromagnetic radiation in the presence of a plasma catalyst, and sustaining the plasma at least until the first and second joining areas are joined. Plasma catalysts, and methods and apparatus for igniting, modulating, and sustaining a joining plasma, are provided. Additional cavity shapes, and methods and apparatus for selective plasma-joining, are also provided.

Abstract: Plasma-assisted methods and apparatus that use multiple radiation sources are provided. In one embodiment, a plasma is ignited by subjecting a gas in a processing cavity to electromagnetic radiation having a frequency less than about 333 GHz in the presence of a plasma catalyst, which may be passive or active. A controller can be used to delay activation of one radiation source with respect to another.

Abstract: Apparatus for suppressing fluid-borne noise in a fluid conduit (12 or 12a) that includes a vibration sensor (36, 36a or 36b) for operative coupling to the conduit for providing an electrical sensor signal as a function of fluid pressure fluctuations in the conduit. A piezoelectric actuator (40, 40a or 40b) is adapted to be mounted on the conduit for imparting pressure fluctuations to fluid in the conduit. An electronic controller (38, 38a or 38b) is responsive to the sensor signal for energizing the actuator 180° out of phase with fluid pressure fluctuations sensed by the sensor. The sensor may be either closely coupled to the actuator, or separate from the actuator and disposed upstream of the actuator with respect to the direction of fluid flow through the conduit. The sensor in the preferred embodiments of the invention comprises a piezoelectric sensor, and the actuator comprises a stack of piezoelectric elements.

Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus. The silicon-containing hydrocarbon compound includes a cyclosiloxan compound or a linear siloxan compound, as a basal structure, with reactive groups for form oligomers using the basal structure. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a. low dielectric constant.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract: A method and apparatus are provided for treating the surface of a metal body through phase transformation, ion implantation, and/or diffusion and to form new phases of metallic materials. The method and apparatus have been shown to be particularly useful to improve the hardness and corrosion resistance of ferrous and non-ferrous metals. Generally, the method comprises irradiating a portion of the metal body (18) with a laser (12), and directing a stream of gas (22) onto the same portion of the metal body simultaneously with and preferably for a duration after the laser is turned off. Preferably, the laser (12) is a carbon dioxide laser operated in a pulsed mode to control heating of the metal (18). The gas (22) is preferably carbon dioxide to quickly cool the metal when the laser is off, and to provide carbon atoms for deposition onto the body.

Abstract: Single wafer processing methods and systems for manufacturing films having low-k properties and low indices of refraction. The methods incorporate a processing station in which both curing and post-cure, in situ gas cooling take place.

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract: A processing chamber and methods for employing this processing chamber to thermally treat wafer-like objects. The chamber comprises a double walled shell, a pedestal style heater, internal passages for the transport of cooling gases and removal of exhaust gases, independently variable gas introduction patterns, and a movable door for sealing the chamber. The chamber is designed to permit in situ cooling of wafer-like objects and to provide means for precise optimization of this cooling. The methods provide for the processing of the wafer-like object in an environment where the temperature, rate of change of the temperature, composition of gases and the relative timings of changes to these variables may be controlled to achieve the desired material properties in the wafer-like object or in films contained on this wafer-like object.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Abstract: A process for preparing S-(&ohgr;-aminoalkylamino) alkyl aryl sulfide dihydrochlorides includes the steps of (a) reacting aryl mercaptan and (&ohgr;-aminoalkylamino) alkylbromide dihydrobromide to cause condensation thereof in the presence of an organic base in an organic solvent and provide a condensation product; (b) converting the condensation product to a dihydrochloride salt; and (c) precipitating the dihydrochloride salt. Preferably the precipitated dihydrochloride salt is recrystallized. These dihydrochlorides are new and effective antidotes for sulfur mustard toxicity.

Abstract: A processing chamber and methods for employing this processing chamber to thermally treat wafer-like objects. The chamber comprises a double walled shell, a pedestal style heater, internal passages for the transport of cooling gases and removal of exhaust gases, independently variable gas introduction patterns, and a movable door for sealing the chamber. The chamber is designed to permit in situ cooling of wafer-like objects and to provide means for precise optimization of this cooling. The methods provide for the processing of the wafer-like object in an environment where the temperature, rate of change of the temperature, composition of gases and the relative timings of changes to these variables may be controlled to achieve the desired material properties in the wafer-like object or in films contained on this wafer-like object.

Abstract: A processing chamber and methods for employing this processing chamber to thermally treat wafer-like objects. The chamber comprises a double walled shell, a pedestal style heater, internal passages for the transport of cooling gases and removal of exhaust gases, independently variable gas introduction patterns, and a movable door for sealing the chamber. The chamber is designed to permit in situ cooling of wafer-like objects and to provide means for precise optimization of this cooling. The methods provide for the processing of the wafer-like object in an environment where the temperature, rate of change of the temperature, composition of gases and the relative timings of changes to these variables may be controlled to achieve the desired material properties in the wafer-like object or in films contained on this wafer-like object.

Abstract: A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.

Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200° C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Abstract: An SOI substrate and method of forming is described incorporating the steps of implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250° C. and above 1300° C., respectively, at two respective oxygen concentrations. The invention overcomes the problem of high SOI substrate fabrication cost due to ion implant time and of getting high quality buried oxide (BOX) layers below a thin layer of single crystal silicon.