Patents by Inventor Dheeraj Srinivasan
Dheeraj Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200393985Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.Type: ApplicationFiled: June 29, 2020Publication date: December 17, 2020Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Patent number: 10832779Abstract: Apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: GrantFiled: August 2, 2019Date of Patent: November 10, 2020Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke
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Patent number: 10762974Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: June 3, 2019Date of Patent: September 1, 2020Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Patent number: 10698624Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.Type: GrantFiled: November 1, 2018Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Publication number: 20200167229Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Patent number: 10552254Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.Type: GrantFiled: August 15, 2017Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Publication number: 20190355431Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: June 3, 2019Publication date: November 21, 2019Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Publication number: 20190355422Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: ApplicationFiled: August 2, 2019Publication date: November 21, 2019Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke
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Publication number: 20190332284Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
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Patent number: 10388379Abstract: An apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: GrantFiled: March 21, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke
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Patent number: 10372353Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.Type: GrantFiled: May 31, 2017Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
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Patent number: 10354738Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: September 27, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Publication number: 20190155744Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh, Michael G. Miller, Xiaoxiao Zhang, Jung Sheng Hoei
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Publication number: 20190096494Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Publication number: 20190065095Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.Type: ApplicationFiled: November 1, 2018Publication date: February 28, 2019Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Publication number: 20190056989Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.Type: ApplicationFiled: August 15, 2017Publication date: February 21, 2019Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Patent number: 10163500Abstract: Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For HBRs, a given set of sense conditions can include a discharged bit line of one or more cells that discharged during a previous HBR. For SBRs, a given set of sense conditions can include loading latches of the sense amplifiers for corresponding cells are with sense results of the previous SBR strobe when the corresponding cells discharged during a previous SBR strobe or loading the latches of the sense amplifiers with sense results of a previous HBR when the corresponding cells discharged during the previous HBR.Type: GrantFiled: September 30, 2017Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Erwin E. Yu, William C. Filipiak, Dheeraj Srinivasan
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Publication number: 20180349029Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
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Patent number: 10120604Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states, and a second of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular second one of the target states.Type: GrantFiled: June 13, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Publication number: 20180301193Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage (ADWLSV). An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: ApplicationFiled: March 21, 2017Publication date: October 18, 2018Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke