Abstract: A disclosed example includes generating a first binary value corresponding to a first sensed threshold voltage of a multi-level cell (MLC) memory cell corresponding to a first time at which a bias voltage is applied to a temporary bias cache capacitor of the MLC memory cell; generating a second binary value corresponding to a second sensed threshold voltage of the MLC memory cell corresponding to a second time at which the bias voltage is not applied to the temporary bias cache capacitor of the MLC memory cell; and based on the first and second binary values, selecting whether to program the MLC memory cell using a full program pulse or a partial program pulse.

Abstract: A disclosed example includes generating a first binary value corresponding to a first sensed threshold voltage of a multi-level cell (MLC) memory cell corresponding to a first time at which a bias voltage is applied to a temporary bias cache capacitor of the MLC memory cell; generating a second binary value corresponding to a second sensed threshold voltage of the MLC memory cell corresponding to a second time at which the bias voltage is not applied to the temporary bias cache capacitor of the MLC memory cell; and based on the first and second binary values, selecting whether to program the MLC memory cell using a full program pulse or a partial program pulse.

Abstract: A disclosed example includes selectively precharging first bitlines of first multi-level cell (MLC) memory cells of a wordline without precharging second bitlines of second MLC memory cells of the wordline during a program verify. First strobe state outputs of the first MLC memory cells are obtained based on first sensed threshold voltage levels of the first MLC memory cells sensed at a first time. Second strobe state outputs of the first MLC memory cells are obtained based on second sensed threshold voltage levels of the first MLC memory cells sensed at a second time. Based on the first and second strobe state outputs, a first MLC memory cell of the first MLC memory cells is programmed using a first programming pulse, and a second MLC memory cell of the first MLC memory cells is programmed using a second programming pulse having a relatively higher voltage than the first programming pulse.