Patents by Inventor Di Feng

Di Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11108477
    Abstract: A method and an apparatus for determining a broadcast beam weighted value are provided. The method includes: obtaining an angle path loss spectrum of a target cell at a current moment, where the angle path loss spectrum includes signal path loss values of a target base station in the target cell in a plurality of directions; determining a beam angle power spectrum based on the angle path loss spectrum, where the beam angle power spectrum includes signal transmit powers of the target base station in the plurality of directions, and in the beam angle power spectrum, a signal transmit power in a direction with a relatively large signal path loss value in the angle path loss spectrum is relatively large; determining a broadcast beam weighted value based on the beam angle power spectrum; and forming a target broadcast beam based on the broadcast beam weighted value.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 31, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhimeng Zhong, Jianyao Zhao, Di Feng
  • Publication number: 20210264205
    Abstract: The disclosure provides an image recognition network model training method, including: acquiring a first image feature corresponding to an image set; acquiring a first identity prediction result by using an identity classifier, and acquiring a first pose prediction result by using a pose classifier; obtaining an identity classifier according to the first identity prediction result and an identity tag, and obtaining a pose classifier according to the first pose prediction result and a pose tag; performing pose transformation on the first image feature by using a generator, to obtain a second image feature corresponding to the image set; acquiring a second identity prediction result by using the identity classifier, and acquiring a second pose prediction result by using the pose classifier; and training the generator.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Zheng Ge, Ze Qun Jie, Hao Wang, Zhi Feng Li, Di Hong Gong, Wei Liu
  • Publication number: 20210264136
    Abstract: A face recognition method includes: extracting a first identity feature of a first face image by using a feature extraction module, and extracting a second identity feature of a second face image by using the feature extraction module, wherein the feature extraction module is implemented by using a neural network, and pre-trained in a manner such that a correlation coefficient of training batch data is obtained based on an identity feature and an age feature of a sample face image in the training batch data, and decorrelated training of the identity feature and the age feature is performed on the feature extraction module based on the correlation coefficient; and performing a face recognition based on determining a similarity between faces in the first face image and the second face image according to the first identity feature and the second identity feature.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Wang, Di Hong Gong, Zhi Feng Li, Wei Liu
  • Publication number: 20210106257
    Abstract: The present disclosure provides a wearable device, a signal processing method and a signal processing apparatus, the signal processing method is applied to the wearable device, the wearable device is provided with a biosensor and a motion detector group, and the signal processing method includes the following steps. The human physiological signal collected by the biosensor is acquired, the human physiological signal is divided into multiple signal frames, each of the multiple signal frames corresponds to the time range; for each signal frame, it is determined whether the user wearing the wearable device is in the body motion state according to the body motion signal collected by the motion detector group within the time range corresponding to the signal frame, and when the user wearing the wearable device is not in the body motion state, the signal frame is stored into the preset buffer.
    Type: Application
    Filed: March 18, 2020
    Publication date: April 15, 2021
    Inventors: Kongqiao WANG, Mingxi ZHAO, Di Feng, Wei ZHAO, Guokang ZHU
  • Publication number: 20210095959
    Abstract: A 3D measurement model and the spatial calibration method based on a 1D displacement sensor are proposed. A 3D measurement system based on a fixed 1D displacement sensor is established; then a spatial measurement model based on the 1D displacement sensor is established; and then based on the high precision pose data of the measurement plane and sensor measurement data, spatial calibration constraint equation are established; a weighted iterative algorithms is employed to calculate the extrinsic parameters of the 1D sensor that meet the precision requirements, then the calibration process is completed. A high precision 3D measurement model is established; a 3D measurement model based on a 1D displacement sensor is established, and the calibration method of the measurement model is proposed, which will improve the precision of the 3D measurement model and solve the problem of inaccurate spatial measurement caused by the errors of the sensor extrinsic parameters.
    Type: Application
    Filed: May 15, 2019
    Publication date: April 1, 2021
    Inventors: Wei LIU, Bing LIANG, Mengde ZHOU, Kun LIU, Yang ZHANG, Di FENG, Xintong JIANG, Likun SI, Zhenyuan JIA
  • Publication number: 20200153493
    Abstract: The present disclosure relates to beamforming methods and devices. In one example method, an access network device calculates an uplink channel frequency response, calculates a model parameter in a channel frequency response mathematical model based on the uplink channel frequency response and each uplink subcarrier frequency, where the model parameter has reciprocity on uplink and downlink subcarrier frequencies, constructs a downlink channel frequency response based on the model parameter, the channel frequency response mathematical model, and each downlink subcarrier frequency, calculates a beamforming weight for each downlink subcarrier frequency based on the downlink channel frequency response, and performs downlink beamforming on an antenna array based on the beamforming weight for each downlink subcarrier frequency, where the antenna array is a dual-polarized antenna array or a single-polarized antenna array.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: Zhimeng ZHONG, Di FENG, Xiaomei ZHANG, Jingfeng QU
  • Publication number: 20200083971
    Abstract: Embodiments of this application disclose a method and an apparatus for determining a broadcast beam weighted value. The method includes: obtaining an angle path loss spectrum of a target cell at a current moment, where the angle path loss spectrum includes signal path loss values of a target base station in the target cell in a plurality of directions; determining a beam angle power spectrum based on the angle path loss spectrum, where the beam angle power spectrum includes signal transmit powers of the target base station in the plurality of directions, and in the beam angle power spectrum, a signal transmit power in a direction with a relatively large signal path loss value in the angle path loss spectrum is relatively large; determining a broadcast beam weighted value based on the beam angle power spectrum; and forming a target broadcast beam based on the broadcast beam weighted value.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Zhimeng ZHONG, Jianyao ZHAO, Di FENG
  • Patent number: 9503106
    Abstract: An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that generates sequential timing signals based on a period of the VCO from a frequency divided VCO signal, a frequency-to-voltage converter (FVC) that converts the frequency divided VCO signal into an output voltage, FVCOUT, an internal reference voltage, and a voltage regulator that generates a control voltage, VCOIN, that is fed back to the VCO to lock a frequency of the VCO in the frequency-locked voltage regulated loop.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, Kai Di Feng
  • Patent number: 9252794
    Abstract: An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, David R. Hanson, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9189654
    Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 17, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai Di Feng, Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Publication number: 20150154421
    Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kai Di Feng, Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9013202
    Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Kai Di Feng, Pui Ling Yee
  • Publication number: 20130314119
    Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Kai Di Feng, Pui Ling Yee
  • Publication number: 20130052662
    Abstract: The present invention is a kit and method for detecting and identifying autoantibodies. The invention employs the use of indirect immunofluorescence, imaging flow cytometry and pattern recognition software to automatically identify autoantibodies associated with autoimmune disorders.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: University of Medicine and Dentistry of New Jersey
    Inventors: Betsy J. Barnes, Di Feng, Rivka C. Stone
  • Patent number: 8338920
    Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Nils D. Hoivik, Xuefeng Liu
  • Patent number: 8211756
    Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 8122395
    Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kai Di Feng
  • Patent number: 8086974
    Abstract: In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventor: Kai Di Feng
  • Patent number: 7962322
    Abstract: A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Elie Awad, Mariette Awad, Kai Di Feng
  • Patent number: 7961032
    Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the tr
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Zhijian Yang, Ping-Chuan Wang, Kai Di Feng