Patents by Inventor Di Feng
Di Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7961032Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the trType: GrantFiled: November 30, 2009Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Zhijian Yang, Ping-Chuan Wang, Kai Di Feng
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Patent number: 7962322Abstract: A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.Type: GrantFiled: June 9, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette Awad, Kai Di Feng
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Publication number: 20110128069Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×1e×VCER], VCER=VBER+VCBR, and 1e=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the traType: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijian Yang, Ping-Chuan Wang, Kai Di Feng
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Patent number: 7930664Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: September 20, 2010Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7926015Abstract: In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.Type: GrantFiled: July 21, 2008Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventor: Kai Di Feng
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Publication number: 20110034021Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: September 20, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7886237Abstract: A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.Type: GrantFiled: June 9, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette Awad, Kai Di Feng
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Patent number: 7839163Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: January 22, 2009Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7816945Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: January 22, 2009Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20100261318Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20100182040Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20100182041Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7759789Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.Type: GrantFiled: January 14, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
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Patent number: 7750697Abstract: In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.Type: GrantFiled: July 21, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventor: Kai Di Feng
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Patent number: 7627835Abstract: A design structure for designing, manufacturing, and/or testing a frequency divider and monitoring circuit. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.Type: GrantFiled: June 20, 2007Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: Kai Di Feng, Zhenrong Jin
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Publication number: 20090243674Abstract: In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.Type: ApplicationFiled: July 21, 2008Publication date: October 1, 2009Inventor: Kai Di Feng
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Publication number: 20090243676Abstract: In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator.Type: ApplicationFiled: July 21, 2008Publication date: October 1, 2009Inventor: Kai Di Feng
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Publication number: 20090243675Abstract: In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.Type: ApplicationFiled: July 21, 2008Publication date: October 1, 2009Inventor: Kai Di Feng
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Publication number: 20090179323Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
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Patent number: 7538622Abstract: A system and a method for operating the same. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.Type: GrantFiled: April 4, 2007Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventor: Kai Di Feng