Patents by Inventor Dieter Pierreux

Dieter Pierreux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150892
    Abstract: The current disclosure relates to methods of forming a vanadium nitride-containing layer. The method comprises providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The disclosure further relates to structures and devices comprising the vanadium nitride-containing layer.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Pia Homm Jara, Werner Knaepen, Dieter Pierreux, Bert Jongbloed, Panagiota Arnou, Ren-Jie Chang, Qi Xie, Giuseppe Alessio Verni, Gido van der Star
  • Publication number: 20240133030
    Abstract: A method and system for depositing a material on one or more substrates by atomic layer deposition. The method comprising a step of performing a pulse (1) of a precursor of said material, wherein at least one of the average flow rate (f) and the average partial pressure (r) of said precursor over a first half (2) of the pulse (1) is higher than over a second half (3) of the pulse (1).
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Dieter Pierreux, Theodorus G.M. Oosterlaken
  • Publication number: 20240068097
    Abstract: A substrate processing apparatus configured to from a layer on a plurality of substrates is disclosed. Embodiments of the presently described substrate processing apparatus comprise a process chamber. The process chamber comprises process space for receiving a substrate boat arranged for holding the plurality of substrates. The substrate processing apparatus further comprise a gas delivery assembly comprising at least one gas injector; a gas exhaust assembly comprising two gas outlets. The two gas outlets are positioned at a distance on either side of the at least one gas injector.
    Type: Application
    Filed: August 21, 2023
    Publication date: February 29, 2024
    Inventors: Subir Parui, Werner Knaepen, Dieter Pierreux, Kelly Houben, Herbert Terhorst, Theodorus G.M. Oosterlaken, Angelos Karagiannis
  • Patent number: 11898243
    Abstract: Methods of forming a vanadium nitride-containing layer comprise providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 13, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Pia Homm Jara, Werner Knaepen, Dieter Pierreux, Bert Jongbloed, Panagiota Arnou, Ren-Jie Chang, Qi Xie, Giuseppe Alessio Verni, Gido van der Star
  • Publication number: 20240044003
    Abstract: A wafer boat and a method for forming a layer on a plurality of substrates that are provided in the wafer boat is disclosed. Aspects of the presently described wafer boat comprise at least two wafer boat rods, each of which including at least a first set of slots for holding a plurality of substrates. The wafer boat further includes a plurality of plates, whereby at least one slot of the at least first set of slots is provided in between two neighboring plates.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 8, 2024
    Inventors: Dieter Pierreux, Bert Jongbloed, Didem Ernur
  • Patent number: 11887857
    Abstract: Disclosed are methods and systems for depositing layers comprising vanadium, nitrogen, and element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon. The layers are deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: January 30, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Dieter Pierreux, Bert Jongbloed, Qi Xie, Giuseppe Alessio Verni
  • Patent number: 11851755
    Abstract: A sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to hold at least a first substrate; a precursor distribution and removal system to provide to and remove from the reaction chamber a vaporized first or second precursor; and, a sequence controller operably connected to the precursor distribution and removal system and comprising a memory provided with a program to execute infiltration of an infiltrateable material provided on the substrate when run on the sequence controller by: activating the precursor distribution and removal system to provide and maintain the first precursor for a first period T1 in the reaction chamber; activating the precursor distribution and removal system to remove a portion of the first precursor from the reaction chamber for a second period T2; and, activating the precursor distribution and removal system to provide and maintain the second precursor for a third period T3 in the reaction chamber.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 26, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Jan Willem Maes, Werner Knaepen, Krzysztof Kamil Kachel, David Kurt de Roest, Bert Jongbloed, Dieter Pierreux
  • Publication number: 20230360905
    Abstract: A method for forming a silicon-comprising layer on a substrate may comprise providing the substrate to a process chamber, the process chamber being comprised in a low pressure chemical vapor deposition (LPCVD) furnace. A repetitive deposition cycle is performed. The deposition cycle comprises a first deposition pulse and a second deposition pulse comprising a provision, into the process chamber, of a first precursor and a second precursor, respectively. The deposition cycle further comprises a first purge pulse and a second purge pulse for removing, from the process chamber, a portion of the first precursor and a portion of the second precursor, respectively. The process chamber is maintained, during the deposition cycle, at a process temperature in a range from about 400° C. to about 650° C. and at a first pressure being different from a second pressure, during the first deposition pulse and during the second deposition pulse, respectively.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 9, 2023
    Inventors: Werner Knaepen, Arjen Klaver, Dieter Pierreux, Bert Jongbloed
  • Publication number: 20230335397
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 19, 2023
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido van Der Star, Toshiya Suzuki
  • Publication number: 20230230833
    Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 20, 2023
    Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed, Kelly Houben, Werner Knaepen, Wilco Verweij
  • Publication number: 20230223255
    Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 13, 2023
    Inventors: Steven Van Aerde, Wilco Verweij, Bert Jongbloed, Dieter Pierreux, Kelly Houben, Rami Khazaka, Frederick Aryeetey, Peter Westrom, Omar Elleuch, Caleb Miskin
  • Publication number: 20230223258
    Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 13, 2023
    Inventors: Dieter Pierreux, Kelly Houben, Steven Van Aerde, Wilco Verweij, Bert Jongbloed, Charles Dezelah
  • Publication number: 20230220588
    Abstract: A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 13, 2023
    Inventors: Steven Van Aerde, Wilco Verweij, Dieter Pierreux, Kelly Houben, Bert Jongbloed, Peter Westrom
  • Patent number: 11694892
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: July 4, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido van Der Star, Toshiya Suzuki
  • Publication number: 20230207309
    Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R.A. Van Aerde, Suvi Haukka, Atsuki Fukazawa, Hideaki Fukuda
  • Publication number: 20230175136
    Abstract: The disclosure relates to a substrate processing apparatus, comprising: a first reactor constructed and arranged to process a rack with a plurality of substrates therein; a second reactor constructed and arranged to process a substrate; and, a substrate transfer device constructed and arranged to transfer substrates to and from the first and second reactor. The second reactor may be provided with an illumination system constructed and arranged to irradiate ultraviolet radiation within a range from 100 to 500 nanometers onto a top surface of at least a substrate in the second reactor.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 8, 2023
    Inventors: Dieter Pierreux, Werner Knaepen, Bert Jongbloed, Jeroen Fluit
  • Patent number: 11646204
    Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 9, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Dieter Pierreux, Steven van Aerde, Bert Jongbloed, Kelly Houben, Werner Knaepen, Wilco Verweij
  • Publication number: 20230140283
    Abstract: A semiconductor substrate processing apparatus, comprising a processing chamber, a wafer boat and a plurality of wafer supports. The wafer boat is configured to accommodate a plurality of wafers and is receivable in the processing chamber for depositing a layer on each wafer. The wafer boat comprises at least two wafer boat posts, wherein each wafer boat post comprises a plurality of slots. Each wafer support comprises a support area configured to support at least a circumferential edge of a wafer, and a flange circumferentially surrounding the support area. The flange is receivable in and supported by the slots and has a width to create a distance between the circumferential edge of the wafer and the wafer boat posts. The distance is such that the wafer boat posts do substantially not influence a layer thickness of the layer which is deposited on the wafer during processing of the wafer.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 4, 2023
    Inventors: Theodorus G.M. Oosterlaken, Dieter Pierreux
  • Patent number: 11629407
    Abstract: The disclosure relates to a substrate processing apparatus, comprising: a first reactor constructed and arranged to process a rack with a plurality of substrates therein; a second reactor constructed and arranged to process a substrate; and, a substrate transfer device constructed and arranged to transfer substrates to and from the first and second reactor. The second reactor may be provided with an illumination system constructed and arranged to irradiate ultraviolet radiation within a range from 100 to 500 nanometers onto a top surface of at least a substrate in the second reactor.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 18, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Dieter Pierreux, Werner Knaepen, Bert Jongbloed, Jeroen Fluit
  • Patent number: 11610775
    Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 21, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R. A. Van Aerde, Suvi Haukka, Atsuki Fukazawa, Hideaki Fukuda