Patents by Inventor Dinesh Patil
Dinesh Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960418Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: GrantFiled: October 13, 2022Date of Patent: April 16, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Patent number: 11951880Abstract: A vehicle seat has a seat base, a carriage, and an adjusting device. The adjusting device is formed in such a way that the vehicle seat is adjustable vertically or the inclination is adjustable by the adjusting device. The adjusting device has a rotation device arranged on the carriage such that the seat base is rotatable relative to the carriage about a vertical axis by the rotation device. The adjusting device includes a strut, a first end of which is pivotably attached to the carriage or to a rotation base fixed to the carriage and a second end of which is pivotably attached to the seat base. The adjusting device has first and second linear actuators. The seat base is supported on the first linear actuator, the second linear actuator, and/or the strut. The first and second linear actuators cooperate to adjust the vehicle seat.Type: GrantFiled: December 2, 2019Date of Patent: April 9, 2024Assignee: MERCEDES-BENZ GROUP AGInventors: Dinesh Lohar, Varad Limaye, Almar Teubert, Ulrich Lasi, Bapusaheb Patil
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Patent number: 11948654Abstract: A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.Type: GrantFiled: May 5, 2022Date of Patent: April 2, 2024Assignee: Meta Platforms Technologies, LLCInventors: Shrirang Madhav Yardi, Dinesh Patil, Neeraj Upasani
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Publication number: 20240102242Abstract: A system and method for labelling normal and abnormal regions in data related to a paper machine for web break prediction and labelling individual parameters for root cause analysis, using machine learning models, includes using the machine learning models in real-time to predict breaks in the paper web, analyzing root cause for the breaks in the paper web, and estimating a time to break. An auto-data-labeling framework helps in adaptive learning for autonomous model improvement of the deployed model, transfer learning, shortlisting parameters and automating feasibility study.Type: ApplicationFiled: November 24, 2022Publication date: March 28, 2024Applicant: ABB Schweiz AGInventors: Vadthyavath Ramu, Dinesh Patil, Nandkishor Kubal
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Publication number: 20240030696Abstract: Techniques for distance protection of a transmission line include determining a fault inception time from a voltage and/or current, determining rate of change sample values indicative of a rate of change of the voltage and/or of a rate of change of the current for at least one sample time that is dependent on the fault inception time, and using the rate of change sample values to generate a phase classifier for fault classification of a zone classifier for faulted zone identification.Type: ApplicationFiled: April 22, 2022Publication date: January 25, 2024Inventors: OD NAIDU, Dinesh PATIL, Neethu GEORGE, Vedanta PRADHAN, Suresh MATURU
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Patent number: 11775448Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.Type: GrantFiled: October 20, 2022Date of Patent: October 3, 2023Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Sudhir Satpathy, Wojciech Stefan Powiertowski, Neeraj Upasani, Dinesh Patil
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Publication number: 20230252156Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.Type: ApplicationFiled: April 6, 2023Publication date: August 10, 2023Inventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
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Patent number: 11636210Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.Type: GrantFiled: September 1, 2020Date of Patent: April 25, 2023Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
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Patent number: 11637916Abstract: The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.Type: GrantFiled: December 3, 2021Date of Patent: April 25, 2023Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Publication number: 20230120661Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: ApplicationFiled: October 13, 2022Publication date: April 20, 2023Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Patent number: 11601532Abstract: In an example of the described techniques, a wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.Type: GrantFiled: April 28, 2020Date of Patent: March 7, 2023Assignee: Meta Platforms Technologies, LLCInventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Publication number: 20230053821Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.Type: ApplicationFiled: October 20, 2022Publication date: February 23, 2023Inventors: Sudhir Satpathy, Wojciech Stefan Powiertowski, Neeraj Upasani, Dinesh Patil
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MACHINE LEARNING BASED METHOD AND DEVICE FOR DISTURBANCE CLASSIFICATION IN A POWER TRANSMISSION LINE
Publication number: 20220413032Abstract: The present specification provides a method and device for determining a disturbance condition in a power transmission line. The method includes obtaining (302) a plurality of sample values corresponding to an electrical parameter measured in each phase. The method further includes determining (304) a plurality of magnitudes of the electrical parameter corresponding to each phase based on the corresponding plurality of sample values and determining (306) a plurality of difference values for each phase based on the corresponding plurality of magnitudes. The method includes processing (308) the plurality of difference values using a machine learning technique to determine the disturbance condition. The disturbance condition is one of a load change condition, a power swing condition and an electrical fault condition. The method also includes performing (310) at least one of a protection function and a control function based on the disturbance condition.Type: ApplicationFiled: November 18, 2020Publication date: December 29, 2022Inventors: Obbalareddi Demudu NAIDU, Dinesh PATIL, Preetham Venkat YALLA -
Patent number: 11520707Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.Type: GrantFiled: November 25, 2019Date of Patent: December 6, 2022Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Sudhir Satpathy, Wojciech Stefan Powiertowski, Neeraj Upasani, Dinesh Patil
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Publication number: 20220350390Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: May 19, 2022Publication date: November 3, 2022Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
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Patent number: 11487679Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: GrantFiled: October 27, 2020Date of Patent: November 1, 2022Assignee: Rambus Inc.Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Patent number: 11340686Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: August 26, 2020Date of Patent: May 24, 2022Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
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Patent number: 11316726Abstract: Receiver circuitries having multiple branches, such as unrolled feedback equalizers and fractional-rate receivers, may present differences between filtering elements of different branches with common filter inputs. Embodiments include devices capable of calibration that compensates such differences. The devices may be capable of introducing front-end offsets to emphasize the mismatches, and sweep filter input values to calculate the mismatches, and introducing offsets in the branches to compensate for the mismatches. Methods for use of the calibration devices are also described.Type: GrantFiled: June 27, 2018Date of Patent: April 26, 2022Assignee: Intel CorporationInventors: Dinesh Patil, Jihong Ren, Reza Navid
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Publication number: 20220094770Abstract: The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Inventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Publication number: 20220004639Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.Type: ApplicationFiled: September 1, 2020Publication date: January 6, 2022Applicant: Facebook Technologies, LLCInventors: Shrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil