Patents by Inventor Dinesh Patil

Dinesh Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10082541
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 25, 2018
    Assignee: Altera Corporation
    Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
  • Patent number: 10031182
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 24, 2018
    Assignee: Altera Corporation
    Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
  • Publication number: 20180041328
    Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Applicant: Altera Corporation
    Inventors: Dinesh Patil, Kok Hong Chan, Wai Tat Wong, Chuan Thim Khor
  • Publication number: 20170308144
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Application
    Filed: May 8, 2017
    Publication date: October 26, 2017
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 9645631
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 9, 2017
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Publication number: 20170097905
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 6, 2017
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Publication number: 20170092586
    Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Applicant: ALTERA CORPORATION
    Inventor: Dinesh PATIL
  • Patent number: 9595495
    Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 14, 2017
    Assignee: Altera Corporation
    Inventor: Dinesh Patil
  • Publication number: 20170052584
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Application
    Filed: August 26, 2016
    Publication date: February 23, 2017
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Publication number: 20160363626
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
    Type: Application
    Filed: June 11, 2015
    Publication date: December 15, 2016
    Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
  • Patent number: 9520324
    Abstract: An integrated circuit system, and a method of manufacture thereof, includes an integrated circuit package connected to a package interconnect connectible to an external resistor, wherein the integrated circuit package includes a master integrated circuit and a slave integrated circuit, the master integrated circuit is connectible to the external resistor and the slave integrated circuit, the master integrated circuit includes a master constant current and a slave constant current, the master constant current flows through the external resistor, and the slave constant current is based on the master constant current.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 13, 2016
    Assignee: Altera Corporation
    Inventors: Dinesh Patil, Minqing Cai
  • Publication number: 20160339411
    Abstract: The present invention discloses activated carbon-metal organic framework composite materials (AC@MOF) with enhanced gas adsorption capacity. The present invention also discloses a process for the preparation of carbon-metal organic framework composite materials (AC@MOF). The present invention involves the use of “void space filling method” in metal organic frameworks (MOFs), which have been accomplished by in-situ addition of selected type and appropriate amount of activated carbon during the synthesis of MOF such as Cu-BTC, in the storage of gases such as methane. The gas adsorption capacity of these AC@MOF composite materials is significantly increased through this method.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Hari C. Bajaj, Rajesh S. Somani, Phani B. Rallapalli, Dinesh Patil, Karikkethu P. Prasanth, Checkalazhikathu R. Manoj, Rajendra S. Thakur, Mathew John, Bharat L. Newalkar, Nettem V. Choudary
  • Patent number: 9501433
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: November 22, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Patent number: 9433919
    Abstract: The present invention discloses activated carbon-metal organic framework composite materials (AC@MOF) with enhanced gas adsorption capacity. The present invention also discloses a process for the preparation of carbon-metal organic framework composite materials (AC@MOF). The present invention involves the use of “void space filling method” in metal organic frameworks (MOFs), which have been accomplished by in-situ addition of selected type and appropriate amount of activated carbon during the synthesis of MOF such as Cu-BTC, in the storage of gases such as methane. The gas adsorption capacity of these AC@MOF composite materials is significantly increased through this method.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 6, 2016
    Assignees: Council of Scientific & Industrial Research, Bharat Petroleum Corporation Limited
    Inventors: Hari Chand Bajaj, Rajesh Shantilal Somani, Phani Brahma Rallapalli, Dinesh Patil, Karikkethu Prabhakaran Prasanth, Checkalazhikathu Raj Manoj, Rajendra Singh Thakur, Mathew John, Bharat Lakshman Newalkar, Nettem Venkateswarlu Choudary
  • Patent number: 9431089
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: August 30, 2016
    Assignee: Rambus Inc.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
  • Patent number: 9417807
    Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 16, 2016
    Assignee: RAMBUS INC.
    Inventors: Kambiz Kaviani, Amir Amirkhany, Dinesh Patil, Mohammad Hekmat
  • Publication number: 20160041781
    Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 11, 2016
    Inventors: Kambiz Kaviani, Amir Amirkhany, Dinesh Patil, Mohammad Hekmat
  • Patent number: 9158679
    Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 13, 2015
    Assignee: RAMBUS INC.
    Inventors: Kambiz Kaviani, Amir Amirkhany, Dinesh Patil, Mohammad Hekmat
  • Publication number: 20150212953
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Publication number: 20150179248
    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
    Type: Application
    Filed: June 10, 2013
    Publication date: June 25, 2015
    Applicant: RAMBUS INC.
    Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware