Patents by Inventor Dinesh Patil
Dinesh Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11196846Abstract: In an example of the described techniques, a wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.Type: GrantFiled: April 28, 2020Date of Patent: December 7, 2021Assignee: Facebook Technologies, LLCInventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Patent number: 11115177Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.Type: GrantFiled: January 11, 2018Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Yanjing Ke, Dinesh Patil, Tim Tri Hoang
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Publication number: 20210149824Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.Type: ApplicationFiled: November 25, 2019Publication date: May 20, 2021Inventors: Sudhir Satpathy, Wojciech Stefan Powiertowski, Neeraj Upasani, Dinesh Patil
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Publication number: 20210152673Abstract: The disclosure describes wireless communication systems. A wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.Type: ApplicationFiled: April 28, 2020Publication date: May 20, 2021Inventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Publication number: 20210149830Abstract: The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.Type: ApplicationFiled: April 28, 2020Publication date: May 20, 2021Inventors: Dinesh Patil, Wojciech Stefan Powiertowski, Neeraj Upasani, Sudhir Satpathy
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Publication number: 20210141748Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: ApplicationFiled: October 27, 2020Publication date: May 13, 2021Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Publication number: 20210041932Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: August 26, 2020Publication date: February 11, 2021Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
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Patent number: 10831685Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: GrantFiled: August 21, 2019Date of Patent: November 10, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Patent number: 10761587Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: November 16, 2018Date of Patent: September 1, 2020Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
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Patent number: 10591544Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.Type: GrantFiled: July 23, 2018Date of Patent: March 17, 2020Assignee: Altera CorporationInventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
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Publication number: 20200050561Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: ApplicationFiled: August 21, 2019Publication date: February 13, 2020Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Publication number: 20200007379Abstract: Receiver circuitries having multiple branches, such as unrolled feedback equalizers and fractional-rate receivers, may present differences between filtering elements of different branches with common filter inputs. Embodiments include devices capable of calibration that compensates such differences. The devices may be capable of introducing front-end offsets to emphasize the mismatches, and sweep filter input values to calculate the mismatches, and introducing offsets in the branches to compensate for the mismatches. Methods for use of the calibration devices are also described.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: Dinesh Patil, Jihong Ren, Reza Navid
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Patent number: 10439615Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.Type: GrantFiled: January 14, 2019Date of Patent: October 8, 2019Assignee: Altera CorporationInventors: Dinesh Patil, Kok Hong Chan, Wai Tat Wong, Chuan Thim Khor
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Patent number: 10402352Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.Type: GrantFiled: October 24, 2016Date of Patent: September 3, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
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Publication number: 20190215146Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Applicant: Intel CorporationInventors: Yanjing Ke, Dinesh Patil, Tim Tri Hoang
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Publication number: 20190171272Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: November 16, 2018Publication date: June 6, 2019Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
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Publication number: 20190149154Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Inventors: Dinesh PATIL, Kok Hong CHAN, Wai Tat WONG, Chuan Thim KHOR
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Patent number: 10218360Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.Type: GrantFiled: August 2, 2016Date of Patent: February 26, 2019Assignee: Altera CorporationInventors: Dinesh Patil, Kok Hong Chan, Wai Tat Wong, Chuan Thim Khor
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Publication number: 20190018063Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.Type: ApplicationFiled: July 23, 2018Publication date: January 17, 2019Applicant: Altera CorporationInventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
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Patent number: 10133338Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: May 8, 2017Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware