Patents by Inventor Dinesh Somasekhar
Dinesh Somasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230110247Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.Type: ApplicationFiled: October 31, 2022Publication date: April 13, 2023Applicant: Intel CorporationInventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
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Publication number: 20220399893Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Chinmay Joshi, Dinesh Somasekhar
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Patent number: 11476185Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.Type: GrantFiled: April 1, 2017Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: MD Altaf Hossain, Dinesh Somasekhar, Dheeraj Subbareddy
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Publication number: 20210407618Abstract: Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Aravinda Radhakrishnan, Marcus Wing-Kin Cheung, Dinesh Somasekhar, Naga Mallika Bhandaru, Michael Nelms, Rodrigo Gonzalez Gutierrez, Kaitlyn Chen
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Patent number: 11152060Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.Type: GrantFiled: June 21, 2019Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Xiaofei Wang, Dinesh Somasekhar, Clifford Ong, Eric A Karl, Zheng Guo, Gordon Carskadon
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Publication number: 20210066178Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Dinesh Somasekhar
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Patent number: 10884853Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.Type: GrantFiled: January 16, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu
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Publication number: 20200402574Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.Type: ApplicationFiled: June 21, 2019Publication date: December 24, 2020Inventors: Xiaofei Wang, Dinesh Somasekhar, Clifford Ong, Eric A Karl, Zheng Guo, Gordon Carskadon
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Patent number: 10860419Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.Type: GrantFiled: December 28, 2018Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Vivek Kozhikkottu, Melin Dadual
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Patent number: 10862622Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.Type: GrantFiled: May 23, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual
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Patent number: 10853300Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.Type: GrantFiled: March 31, 2017Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar
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Publication number: 20200313694Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K?2(K?1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Wei Wu, Vivek Kozihikkottu, Dinesh Somasekhar, Jon Stephan, Kon-Woo Kwon
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Publication number: 20200210284Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Vivek Kozhikkottu, Melin Dadual
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Publication number: 20200176372Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.Type: ApplicationFiled: April 1, 2017Publication date: June 4, 2020Inventors: MD Altaf HOSSAIN, Dinesh SOMASEKHAR, Dheeraj SUBBAREDDY
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Publication number: 20190303159Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Joshua B. FRYMAN, Jason M. HOWARD, Priyanka SURESH, Banu Meenakshi NAGASUNDARAM, Srikanth DAKSHINAMOORTHY, Ankit MORE, Robert PAWLOWSKI, Samkit JAIN, Pranav YEOLEKAR, Avinash M. SEEGEHALLI, Surhud KHARE, Dinesh SOMASEKHAR, David S. DUNNING, Romain E. Cledat, William Paul GRIFFIN, Bhavitavya B. BHADVIYA, Ivan B. GANEV
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Publication number: 20190280813Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Applicant: Intel CorporationInventors: Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual
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Patent number: 10347309Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.Type: GrantFiled: February 22, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Ashoke Ravi, Dinesh Somasekhar, Ganesh Balamurugan, Sudip Shekhar, Tawfiq Musah, Tzu-Chien Hsueh
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Patent number: 10319461Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.Type: GrantFiled: June 29, 2016Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Kon-Woo Kwon, Vivek Kozhikkottu, Dinesh Somasekhar
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Publication number: 20190146873Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.Type: ApplicationFiled: January 16, 2019Publication date: May 16, 2019Inventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu
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Patent number: RE49439Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.Type: GrantFiled: December 4, 2019Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar