Patents by Inventor Dinesh Somasekhar

Dinesh Somasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200210284
    Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Vivek Kozhikkottu, Melin Dadual
  • Publication number: 20200176372
    Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.
    Type: Application
    Filed: April 1, 2017
    Publication date: June 4, 2020
    Inventors: MD Altaf HOSSAIN, Dinesh SOMASEKHAR, Dheeraj SUBBAREDDY
  • Publication number: 20190303159
    Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Joshua B. FRYMAN, Jason M. HOWARD, Priyanka SURESH, Banu Meenakshi NAGASUNDARAM, Srikanth DAKSHINAMOORTHY, Ankit MORE, Robert PAWLOWSKI, Samkit JAIN, Pranav YEOLEKAR, Avinash M. SEEGEHALLI, Surhud KHARE, Dinesh SOMASEKHAR, David S. DUNNING, Romain E. Cledat, William Paul GRIFFIN, Bhavitavya B. BHADVIYA, Ivan B. GANEV
  • Publication number: 20190280813
    Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual
  • Patent number: 10347309
    Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Ashoke Ravi, Dinesh Somasekhar, Ganesh Balamurugan, Sudip Shekhar, Tawfiq Musah, Tzu-Chien Hsueh
  • Patent number: 10319461
    Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Kon-Woo Kwon, Vivek Kozhikkottu, Dinesh Somasekhar
  • Publication number: 20190146873
    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu
  • Publication number: 20190115293
    Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Inventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Dinesh Somasekhar
  • Publication number: 20180285304
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar
  • Patent number: 9998401
    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Surhud Khare, Ankit More, Dinesh Somasekhar, David S. Dunning
  • Patent number: 9992135
    Abstract: Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Surhud Khare, Dinesh Somasekhar, Ankit More, David S. Dunning, Nitin Y. Borkar, Shekhar Y. Borkar
  • Patent number: 9948179
    Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Patent number: 9870012
    Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Publication number: 20180004597
    Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Kon-Woo KWON, Vivek KOZHIKKOTTU, Dinesh SOMASEKHAR
  • Patent number: 9837391
    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
  • Publication number: 20170286216
    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to read K bits of M bits of encoded data in memory, D error detection bits, and P Parity bits protecting the M bits of encoded data for performing a read-write-modify (RWM) command operation on the K bits of the M bits encoded data, wherein K, M and D are positive integers and P is a vector of a set of parity bits. The memory controller can determine whether an error is present on the K bits of the M bits of encoded data according to the D error detection bits.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Vivek Kozhikkottu, Dinesh Somasekhar, Young Moon Kim, Sang Phill Park
  • Publication number: 20170229161
    Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 10, 2017
    Inventors: Jaydeep P. Kulkarni, Ashoke Ravi, Dinesh Somasekhar, Ganesh Balamurugan, Sudip Shekhar, Tawfiq Musah, Tzu-Chien Hsueh
  • Publication number: 20170170153
    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
  • Publication number: 20170171111
    Abstract: Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Surhud Khare, Dinesh Somasekhar, Ankit More, David S. Dunning, Nitin Y. Borkar, Shekhar Y. Borkar
  • Patent number: 9621163
    Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Amit R. Trivedi, Jaydeep P. Kulkarni, Dinesh Somasekhar, Muhammad M. Khellah, Carlos Tokunaga, James W. Tschanz