Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: An apparatus for electroless plating includes a plating bath containing an aqueous metal salt solution, and a magnetic field generator for generating a magnetic field. An object to be plated is immersed in the solution. The magnetic field generated by the magnetic field generator increases the level at which the metal ions are attracted to a surface of the object. Therefore, a layer of plating of good quality may be formed at a rapid rate.

Abstract: A semiconductor package and associated methods, the semiconductor package including a substrate including a socket, and connection terminals including a solder ball and a supporting portion extending from the solder ball into the socket.

Abstract: Example embodiments may be directed to a printed circuit board having an insulating substrate, pads disposed on the surface of the insulating substrate, a solder resist, and a solder moving portion. Leads of a semiconductor package may be mounted on the insulating substrate. The pads to which the leads of the semiconductor package are connected may be disposed on the surface of the insulating substrate. The solder resist layer may cover the insulating substrate, but may also contain openings exposing at least a portion of the pads to which the leads of the semiconductor package are connected. During the process by which each semiconductor lead is connected to a pad, the solder moving portion on the pad may allow an adhesion solder coating each of the leads of the semiconductor package to move towards a shoulder portion of the semiconductor package leads.

Abstract: A semiconductor module and a method of manufacturing a semiconductor module including at least one chip package, at least one module board, at least one conductive element provided between the first chip package and the module board and a protector for applying pressure to the conductive element, the module board, and the first chip package and/or acting as a heat sink for the first chip package.

Abstract: A heat spreader includes a heat sinking plate and a pressure clip. The heat sinking plate radiates the heat away from a heat source. The pressure clip fixes the heat sinking plate to the heat source. The pressure clip includes a spine (pressing part), one or more ribs and hook parts. The spine is arranged on the heat sinking plate. The one or more ribs extend from the spine and contact the heat source. The hook parts extend from the spine and are supported by the heat source. The pressure clip further includes mounting parts that couple the spine to the hook parts. A bending space is formed between the spine and the heat sinking plate. The heat spreader may be attached to a printed circuit board (PCB) with, e.g., a one-touch method, so that assembling processes of the memory module may be automated.

Abstract: A PCB can include an insulating member, a cooling member, and a circuit pattern. The cooling member can be built into the insulating member. The cooling member can have a cooling passageway through which a cooling fluid can flow. The circuit pattern can be formed on the insulating member. Thus, high heat in the circuit pattern can be rapidly dissipated by the cooling fluid flowing through the cooling passageway.

Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.

Abstract: A semiconductor module includes a base plate, a circuit substrate coupled to a side face of the base plate, a first semiconductor package mounted on the circuit substrate and a radiation channel portion inside the base plate. The radiation channel portion includes at least one heat pipe containing a working fluid. The at least one heat pipe containing the working fluid is configured to transfer heat generated by the first semiconductor package. Thus, the radiation channel portion may provide an efficient and reliable semiconductor module having improved heat transfer and radiation performance.

Abstract: Example embodiments of the present invention include a printed circuit board (PCB) capable of controlling the size and position of voids during a surface mounting process. To this end, the PCB includes: an insulating plate made of an insulating material; printed circuit patterns formed on the insulating plate; a plurality of lands to support a plurality of solder joints, each land coupled to one end of each of the printed circuit patterns; and anti-wetting layers mounted on a surface of each of the lands for solder joint therein. The anti-wetting layers allow a void produced during a surface mounting process to move to a central surface on a pad, so that the solder joint reliability between the solder ball and the land is increased. As a result, the reliability of a semiconductor device is enhanced.

Abstract: Provided are a semiconductor package and a module printed circuit board (PCB) for mounting the same. Each of the semiconductor package and the module PCB includes a substrate, a first-type pad structure disposed in a first region of the substrate, and a second-type pad structure disposed in a second region of the package substrate. The first-type pad includes a first conductive pad disposed on the package substrate and a first insulating layer coated on the package substrate. The first insulating layer has a first opening by which a portion of a sidewall of the first conductive pad is exposed, and partially covers the first conductive pad. The second-type pad includes a second insulating layer coated on the package substrate to have a second opening and a second conductive pad disposed on the package substrate in the second opening to have an exposed sidewall.

Abstract: Provided are a chip network resistor contacting a printed circuit board (PCB) through solder balls and a semiconductor module having the chip network resistor. The chip network resistor includes: a body formed of an insulating material; a resistor formed on the body; external electrodes connected to the resistor and disposed on a lower surface of the body so as to have solder ball pad shapes; and conductive balls adhered on the external electrodes.

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: A reworkable passive element embedded printed circuit board (PCB) including a board member, first and second fillings, and a first passive element. The board member has first and second through holes which are spaced apart from each other. The first and second fillings are buried in the first and second through holes, respectively, and formed of a reflowable conductive material. The first passive element includes first and second electrodes. A first insertion groove is formed in a portion of a surface of the board member between the first and second through holes and portions of the first and second fillings. The first passive element is mounted on the first insertion groove. The first electrode includes a bottom surface and a side contacting the first filling and an exposed upper surface. The second electrode comprises a bottom surface and a side contacting the second filling and an exposed upper surface.

Abstract: A lead frame type stack package in which a lead of the package is well connected to a semiconductor module, and a method of fabricating the same are provided. A lead of an upper package and a lead of a lower package are connected using laser soldering. Since leads of the upper and lower packages are connected by solder balls without the use of a soldering pot, loss of a plating layer of the lead due to solder dipping is prevented and the leads are well connected without soldering defects when connecting the lead of the lower package to a connection pad of a semiconductor module substrate.

Abstract: A method and arrangement for attaching labels to a plurality of semiconductor modules arranged on a double-sided substrate is described which may shorten a process stream in an effort to reduce equipment costs. An exemplary arrangement may include at least one label attaching unit configured to attach labels to a plurality of semiconductor modules mounted on one of a first surface and a second surface of the double-sided substrate, and may include at least one turner configured to turn over the double-sided substrate to expose one of the first surface and second surface to the label attaching unit.

Abstract: A semiconductor package may include a substrate having external contact terminals. A semiconductor chip having bonding pads may be formed on the substrate. Conductive bumps may connect the external contact terminals of the substrate to the bonding pads of the semiconductor chip. An underfill may be interposed between the substrate and the semiconductor chip. The underfill may include a first underfill region composed of a first material adjacent to the semiconductor chip and a second underfill region composed of a second material adjacent to the substrate, the first material having a higher glass transition temperature than the second material.

Abstract: Example embodiments relate to a semiconductor package. The semiconductor package may include a mounting substrate, a semiconductor chip mounted to the mounting substrate, at least one passive component passing therethrough and mounted to the mounting substrate, and a cover covering the mounting substrate, the semiconductor chip and the at least one passive component.

Abstract: For an automatic defect inspection of an edge exposure area of a wafer, an optical unit supplies a light beam onto the edge portion of a wafer and a detection unit detects light reflected from the edge portion. The detection unit converts the detected light into an electrical signal to transmit the electrical signal to a processing unit. The processing unit analyzes the electrical signal to measure the reflectivity of the edge portion, compares the measured reflectivity with a reference reflectivity, and calculates the width of the edge exposure area. The processing unit compares the calculated width with a reference width to detect any defect in the edge exposure area.

Abstract: An apparatus for inspecting a semiconductor device may include an external image detector to acquire an exterior image of the semiconductor device, an internal image detector to acquire an interior image of the semiconductor device, and a controller to compare the acquired images with respective references. The apparatus may both inspect the exterior and the interior of the semiconductor device.